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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Ivy Bridge (microarchitecture)</span></span>
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</style><div role="note" class="hatnote navigation-not-searchable">This article is about the Intel microarchitecture. For other uses, see <a href="Ivy_Bridge_(disambiguation)" class="mw-redirect mw-disambig" title="Ivy Bridge (disambiguation)">Ivy Bridge</a>.</div>
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</style><table class="infobox"><caption class="infobox-title">Ivy Bridge</caption><tbody><tr><td colspan="2" class="infobox-image"><span typeof="mw:File"></span><div class="infobox-caption">Intel's internal Ivy Bridge logo<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">April 29, 2012<span style="display:none"> (<span class="bday dtstart published updated">April 29, 2012</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">June 5, 2015<span style="display: none;"> (<span class="dtend">2015-06-05</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">
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</style><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">0306A9h</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80633 (extreme desktop) <br> 80634 (server LGA1356) <br> 80635 (server E5 LGA2011) <br> 80636 (server E7 LGA2011) <br> 80637 (desktop) <br> 80638 (mobile)</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.4 to 4.1<span class="nowrap"> </span>GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="Direct_Media_Interface" title="Direct Media Interface">DMI</a> speeds</th><td class="infobox-data">4 GT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">64<span class="nowrap"> </span><a href="Kibibyte" class="mw-redirect" title="Kibibyte">KB</a> per core (32<span class="nowrap"> </span>KB instructions + 32<span class="nowrap"> </span>KB data)</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256<span class="nowrap"> </span>KB per core</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">2 to 37.5<span class="nowrap"> </span>MB shared</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">Intel <a href="22_nm_process" title="22 nm process">22 nm</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="IA-32" title="IA-32">IA-32</a>, <a href="X86-64" title="X86-64">x86-64</a></td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="SSE2" title="SSE2">SSE2</a>, <a href="SSE3" title="SSE3">SSE3</a>, <a href="SSSE3" title="SSSE3">SSSE3</a>, <a href="SSE4" title="SSE4">SSE4</a>, <a href="SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="F16C" title="F16C">F16C</a></li><li><a href="AES_instruction_set" title="AES instruction set">AES-NI</a>, <a href="CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="RDRAND" title="RDRAND">RDRAND</a>, <a href="Trusted_Execution_Technology" title="Trusted Execution Technology">TXT</a></li><li><a href="Intel_VT-x" class="mw-redirect" title="Intel VT-x">VT-x</a>, <a href="Intel_VT-d" class="mw-redirect" title="Intel VT-d">VT-d</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Transistor_count" title="Transistor count">Transistors</a></th><td class="infobox-data"><div class="plainlist"><ul><li>634 million to 2.104 billion</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><div class="plainlist"><ul><li>2–4 (Mainstream) <br> 2–15 (Xeon)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="Graphics_processing_unit" title="Graphics processing unit">GPUs</a></th><td class="infobox-data"><a href="Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">HD Graphics 2500</a><br>650 to 1150 MHz<br><a href="Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">HD Graphics 4000</a><br>350 to 1300 MHz<br><a href="Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">HD Graphics P4000</a><br>650 to 1250 MHz</td></tr><tr><th scope="row" class="infobox-label">Sockets</th><td class="infobox-data"><div class="plainlist"><ul><li><b>Desktop & Workstation</b> <div><ul><li><a href="LGA_1155" title="LGA 1155">LGA 1155</a></li><li><a href="LGA_2011" title="LGA 2011">LGA 2011</a></li></ul></div></li><li><b>Server</b> <div><ul><li><a href="LGA_2011" title="LGA 2011">LGA 2011</a></li><li><a href="LGA_2011" title="LGA 2011">LGA 2011-1</a></li><li><a href="LGA_1356" title="LGA 1356">LGA 1356</a></li></ul></div></li><li><b>Mobile</b> <div><ul><li><a href="Socket_G2" title="Socket G2">Socket G2</a></li><li>BGA 1023</li><li>BGA 1224</li><li>BGA 1284</li></ul></div></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Models</th><td class="infobox-data"><div class="plainlist"><ul><li>Ivy Bridge-DT</li><li>Ivy Bridge-M</li><li>Ivy Bridge-EN (entry)</li><li>Ivy Bridge-EP (efficient performance)</li><li>Ivy Bridge-EX (expandable)</li><li>Gladden (embedded)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Brand names</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="Celeron" title="Celeron">Celeron</a></li><li><a href="Pentium" title="Pentium">Pentium</a></li><li><a href="Intel_Core" title="Intel Core">Core</a></li><li><a href="Xeon" title="Xeon">Xeon</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> (tock)</td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> (tock/architecture)</td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Unsupported</td></tr></tbody></table>
<p><b>Ivy Bridge</b> is the <a href="List_of_Intel_codenames" title="List of Intel codenames">codename</a> for Intel's <a href="22_nm_process" title="22 nm process">22 nm</a> <a href="Microarchitecture" title="Microarchitecture">microarchitecture</a> used in the third generation of the <a href="Intel_Core" title="Intel Core">Intel Core processors</a> (<a href="Intel_Core_i7" class="mw-redirect" title="Intel Core i7">Core i7</a>, <a href="Intel_Core_i5" class="mw-redirect" title="Intel Core i5">i5</a>, <a href="Intel_Core_i3" class="mw-redirect" title="Intel Core i3">i3</a>). Ivy Bridge is a <a href="Die_shrink" title="Die shrink">die shrink</a> to <a href="22_nanometer" class="mw-redirect" title="22 nanometer">22 nm</a> process based on <a href="FinFET" class="mw-redirect" title="FinFET">FinFET</a> ("3D") <a href="Tri-Gate_transistor" class="mw-redirect" title="Tri-Gate transistor">Tri-Gate transistors</a>, from the former generation's <a href="32_nanometer" class="mw-redirect" title="32 nanometer">32 nm</a> <a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> microarchitecture—also known as <a href="Tick%E2%80%93tock_model" title="Tick–tock model">tick–tock model</a>. The name is also applied more broadly to the <a href="Intel_Xeon" class="mw-redirect" title="Intel Xeon">Xeon</a> and <a href="Core_i7" class="mw-redirect" title="Core i7">Core i7 Extreme</a> <a href="Ivy_Bridge-E" class="mw-redirect" title="Ivy Bridge-E">Ivy Bridge-E</a> series of processors released in 2013.
</p><p>Ivy Bridge processors are <a href="Backward_compatibility" title="Backward compatibility">backward compatible</a> with the Sandy Bridge platform, but such systems might require a firmware update (vendor specific).<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> In 2011, Intel released the 7-series <a href="Panther_Point" class="mw-redirect" title="Panther Point">Panther Point</a> <a href="List_of_Intel_chipsets#5/6/7/8/9_Series_chipsets" title="List of Intel chipsets">chipsets</a> with integrated <a href="USB_3.0" title="USB 3.0">USB 3.0</a> and <a href="SATA_3.0" class="mw-redirect" title="SATA 3.0">SATA 3.0</a> to complement Ivy Bridge.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup>
</p><p>Volume production of Ivy Bridge chips began in the third quarter of 2011.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> <a href="Quad-core" class="mw-redirect" title="Quad-core">Quad-core</a> and dual-core-mobile models launched on April 29, 2012 and May 31, 2012 respectively.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> Core i3 desktop processors, as well as the first 22 nm <a href="Pentium" title="Pentium">Pentium</a>, were announced and available the first week of September 2012.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>
</p><p>Ivy Bridge is the last Intel platform on which Windows older than <a href="Windows_7" title="Windows 7">Windows 7</a> and Windows Server older than <a href="Windows_Server_2008_R2" title="Windows Server 2008 R2">Windows Server 2008 R2</a> are officially supported by <a href="Microsoft" title="Microsoft">Microsoft</a>. It is also the earliest Intel microarchitecture to officially support <a href="Windows_10" title="Windows 10">Windows 10</a> 64-bit (NT 10.0).<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>
</p>
<meta property="mw:PageProp/toc">
<div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2></div>
<p>The Ivy Bridge CPU microarchitecture is a shrink from Sandy Bridge and remains largely unchanged. Like its predecessor, Sandy Bridge, Ivy Bridge was also primarily developed by Intel's Israel branch, located in <a href="Haifa%2C_Israel" class="mw-redirect" title="Haifa, Israel">Haifa, Israel</a>.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> Notable improvements include:<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup>
</p>
<ul><li>New 22 nm <a href="Tri-gate_transistor" class="mw-redirect" title="Tri-gate transistor">Tri-gate transistor</a> ("3-D") technology offer as much as a 50% reduction to power consumption at the same performance level as compared to 2-D planar transistors on Intel's 32 nm process.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup></li>
<li>A new <a href="Pseudorandom_number_generator" title="Pseudorandom number generator">pseudorandom number generator</a> and the <a href="RDRAND" title="RDRAND">RDRAND</a> instruction,<sup id="cite_ref-ieee_spectrum_12-0" class="reference"><a href="#cite_note-ieee_spectrum-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> codenamed Bull Mountain.<sup id="cite_ref-bull_mountain_13-0" class="reference"><a href="#cite_note-bull_mountain-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></li></ul>
<div class="mw-heading mw-heading2"><h2 id="Ivy_Bridge_features_and_performance">Ivy Bridge features and performance</h2></div>
<p>The mobile and desktop Ivy Bridge chips also include some minor yet notable changes over Sandy Bridge:
</p>
<div class="mw-heading mw-heading3"><h3 id="CPU">CPU</h3></div>
<ul><li><a href="F16C" title="F16C">F16C</a> (16-bit floating-point conversion instructions)<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li>
<li><a href="RDRAND" title="RDRAND">RDRAND</a> instruction (Intel Secure Key)<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li>
<li>Max <a href="CPU_multiplier" title="CPU multiplier">CPU multiplier</a> of 63 (versus 57 for Sandy Bridge)<sup id="cite_ref-IB_16-0" class="reference"><a href="#cite_note-IB-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li>
<li><a href="Thermal_design_power#Alternatives" title="Thermal design power">Configurable TDP</a> (cTDP) for mobile processors<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup></li>
<li>A 14- to 19-stage <a href="Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">instruction pipeline</a>, depending on the <a href="Micro-operation_cache" class="mw-redirect" title="Micro-operation cache">micro-operation cache</a> hit or miss<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup></li>
<li><a href="Supervisor_Mode_Execution_Prevention" class="mw-redirect" title="Supervisor Mode Execution Prevention">Supervisor Mode Execution Prevention</a><sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup></li>
<li>CPUID Faulting support<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup></li></ul>
<dl><dd><table class="wikitable" style="text-align: center">
<caption><span class="nowrap"><a href="Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> sizes</span><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup>
</caption>
<tbody><tr>
<th colspan="2">Cache
</th>
<th colspan="3">Page Size
</th></tr>
<tr>
<th>Name
</th>
<th>Level
</th>
<th>4<span class="nowrap"> </span>KB
</th>
<th>2<span class="nowrap"> </span>MB
</th>
<th>1<span class="nowrap"> </span>GB
</th></tr>
<tr>
<td>DTLB
</td>
<td>1st
</td>
<td>64
</td>
<td>32
</td>
<td>4
</td></tr>
<tr>
<td>ITLB
</td>
<td>1st
</td>
<td>128
</td>
<td>8 / logical core
</td>
<td>none
</td></tr>
<tr>
<td>STLB
</td>
<td>2nd
</td>
<td>512
</td>
<td>none
</td>
<td>none
</td></tr></tbody></table></dd></dl>
<div class="mw-heading mw-heading3"><h3 id="GPU">GPU</h3></div>
<ul><li>The built-in <a href="Graphics_processing_unit" title="Graphics processing unit">GPU</a> has 6 or 16 <a href="Execution_units" class="mw-redirect" title="Execution units">execution units</a> (EUs), compared to Sandy Bridge's 6 or 12.<sup id="cite_ref-anandtech_ivy_bridge_23-0" class="reference"><a href="#cite_note-anandtech_ivy_bridge-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></li>
<li><a href="Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">Intel HD Graphics</a> with <a href="DirectX_11" class="mw-redirect" title="DirectX 11">DirectX 11</a>, <a href="OpenGL" title="OpenGL">OpenGL 4.0</a>, and <a href="OpenCL" title="OpenCL">OpenCL 1.2</a> support on Windows.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> On Linux, OpenGL 4.2 is supported since <a href="Mesa_(computer_graphics)" title="Mesa (computer graphics)">Mesa</a> 17.1.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup></li>
<li>Support for up to three displays (with some limitations: with chipset of 7-series and using two of them with DisplayPort or eDP)<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup></li>
<li>Multiple <a href="4K_resolution" title="4K resolution">4K</a> displays video playback</li>
<li><a href="Intel_Quick_Sync_Video" title="Intel Quick Sync Video">Intel Quick Sync Video</a> version 2<sup id="cite_ref-anandtech_ivy_bridge_23-1" class="reference"><a href="#cite_note-anandtech_ivy_bridge-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></li></ul>
<div class="mw-heading mw-heading3"><h3 id="IO">IO</h3></div>
<ul><li>RAM support up to 2800<span class="nowrap"> </span><a href="Megatransfers_per_second" class="mw-redirect" title="Megatransfers per second">MT/s</a> in 200 MHz increments<sup id="cite_ref-IB_16-1" class="reference"><a href="#cite_note-IB-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li>
<li><a href="DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> for mobile CPUs</li>
<li><a href="PCI_Express_3" class="mw-redirect" title="PCI Express 3">PCI Express 3.0</a> support (omitted on Core i3, Pentium, and <a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ultra-low-voltage</a> [ULV] processors)<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup></li></ul>
<div class="mw-heading mw-heading3"><h3 id="Benchmark_comparisons">Benchmark comparisons</h3></div>
<p>Compared to its predecessor, Sandy Bridge:
</p>
<ul><li>3% to 6% increase in CPU performance when compared clock for clock<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></li>
<li>25% to 68% increase in integrated GPU performance<sup id="cite_ref-performance_30-0" class="reference"><a href="#cite_note-performance-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li></ul>
<div class="mw-heading mw-heading3"><h3 id="Thermal_performance_issues">Thermal performance issues</h3></div>
<p>Ivy Bridge's temperatures are reportedly 10<span class="nowrap"> </span>°C higher compared to Sandy Bridge when a CPU is <a href="Overclocking" title="Overclocking">overclocked</a>, even at default voltage setting.<sup id="cite_ref-heat_31-0" class="reference"><a href="#cite_note-heat-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> Impress PC Watch, a Japanese website, performed experiments that confirmed earlier speculations that this is because Intel used a poor quality (and perhaps lower cost) <a href="Thermal_interface_material" title="Thermal interface material">thermal interface material</a> (thermal paste, or "TIM") between the chip and the <a href="Heat_spreader" title="Heat spreader">heat spreader</a>, instead of the <a href="Solder_flux" class="mw-redirect" title="Solder flux">fluxless</a> solder of previous generations.<sup id="cite_ref-vr-zone_32-0" class="reference"><a href="#cite_note-vr-zone-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-techpowerup_33-0" class="reference"><a href="#cite_note-techpowerup-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-cheapTIM_34-0" class="reference"><a href="#cite_note-cheapTIM-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> The mobile Ivy Bridge processors are not affected by this issue because they do not use a heat spreader between the chip and cooling system. Socket 2011 Ivy Bridge processors continue to use the solder.<sup id="cite_ref-thermal2011_35-0" class="reference"><a href="#cite_note-thermal2011-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup>
</p><p>Enthusiast reports describe the TIM used by Intel as low-quality,<sup id="cite_ref-cheapTIM_34-1" class="reference"><a href="#cite_note-cheapTIM-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> and not up to par for a "premium" CPU, with some speculation that this is by design to encourage sales of prior processors.<sup id="cite_ref-vr-zone_32-1" class="reference"><a href="#cite_note-vr-zone-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> Further analyses caution that the processor can be damaged or void its warranty if home users attempt to remedy the matter.<sup id="cite_ref-vr-zone_32-2" class="reference"><a href="#cite_note-vr-zone-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> The TIM has much lower <a href="Thermal_conductivity" class="mw-redirect" title="Thermal conductivity">thermal conductivity</a>, causing heat to trap on the die.<sup id="cite_ref-heat_31-1" class="reference"><a href="#cite_note-heat-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> Experiments with replacing this TIM with a higher-quality one or other heat removal methods showed a substantial temperature drop, and improvements to the increased voltages and overclocking sustainable by Ivy Bridge chips.<sup id="cite_ref-vr-zone_32-3" class="reference"><a href="#cite_note-vr-zone-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup>
</p><p>Intel claims that the smaller die of Ivy Bridge and the related increase in thermal density is expected to result in higher temperatures when the CPU is overclocked; Intel also stated that this is as expected and will likely not improve in future revisions.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading3"><h3 id="Models_and_steppings">Models and steppings</h3></div>
<p>All Ivy Bridge processors with one, two, or four cores report the same CPUID model 0x000306A9, and are built in four different configurations differing in the number of cores, L3 cache and GPU execution units.
</p>
<table class="wikitable sortable">
<tbody><tr>
<th>Die code name
</th>
<th>CPUID
</th>
<th>Stepping
</th>
<th>Die size
</th>
<th>Die dimensions
</th>
<th>Transistors
</th>
<th>Cores
</th>
<th>GPU EUs
</th>
<th>L3 cache
</th>
<th>Sockets
</th></tr>
<tr>
<td>Ivy Bridge-M-2
</td>
<td rowspan="4"><code>0x000306A9</code>
</td>
<td>P0
</td>
<td><span aria-hidden="true" style="visibility:hidden;color:transparent;">0</span>94 mm<sup>2</sup><sup id="cite_ref-Intel_Datasheet_39-0" class="reference"><a href="#cite_note-Intel_Datasheet-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup>
</td>
<td>7.656 × 12.223 mm
</td>
<td><span aria-hidden="true" style="visibility:hidden;color:transparent;">0</span>≈634 million<sup id="cite_ref-transistor-counts_40-0" class="reference"><a href="#cite_note-transistor-counts-40"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup>
</td>
<td rowspan="2">2
</td>
<td>6<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup>
</td>
<td>3<span class="nowrap"> </span>MB<sup id="cite_ref-Ivy_Bridge_Modular_Design_42-0" class="reference"><a href="#cite_note-Ivy_Bridge_Modular_Design-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup>
</td>
<td rowspan="4"><a href="LGA_1155" title="LGA 1155">LGA 1155</a>,<br><a href="Socket_G2" title="Socket G2">Socket G2</a>,<br>BGA-1224,<br>BGA-1023,<br>BGA-1284
</td></tr>
<tr>
<td>Ivy Bridge-H-2
</td>
<td>L1
</td>
<td>118 mm<sup>2</sup><sup id="cite_ref-Intel_Datasheet_39-1" class="reference"><a href="#cite_note-Intel_Datasheet-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup>
</td>
<td>8.141 × 14.505 mm
</td>
<td><span aria-hidden="true" style="visibility:hidden;color:transparent;">0</span>≈830 million<sup id="cite_ref-transistor-counts_40-1" class="reference"><a href="#cite_note-transistor-counts-40"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup>
</td>
<td>16
</td>
<td>4 MB
</td></tr>
<tr>
<td>Ivy Bridge-HM-4
</td>
<td>N0
</td>
<td>133 mm<sup>2</sup><sup id="cite_ref-Intel_Datasheet_39-2" class="reference"><a href="#cite_note-Intel_Datasheet-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup>
</td>
<td>7.656 × 17.349 mm
</td>
<td>≈1008 million<sup id="cite_ref-transistor-counts_40-2" class="reference"><a href="#cite_note-transistor-counts-40"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup>
</td>
<td rowspan="2">4
</td>
<td>6
</td>
<td>6 MB<sup id="cite_ref-Ivy_Bridge_Modular_Design_42-1" class="reference"><a href="#cite_note-Ivy_Bridge_Modular_Design-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup>
</td></tr>
<tr>
<td>Ivy Bridge-HE-4
</td>
<td>E1
</td>
<td>160 mm<sup>2</sup><sup id="cite_ref-Intel_Datasheet_39-3" class="reference"><a href="#cite_note-Intel_Datasheet-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup>
</td>
<td>8.141 × 19.361 mm
</td>
<td>≈1400 million<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup>
</td>
<td>16
</td>
<td>8<span class="nowrap"> </span>MB
</td></tr></tbody></table>
<div class="mw-heading mw-heading2"><h2 id="Ivy_Bridge–based_Xeon_processors">Ivy Bridge–based Xeon processors</h2></div>
<div role="note" class="hatnote navigation-not-searchable">Main article: <a href="Intel_Ivy_Bridge%E2%80%93based_Xeon_microprocessors" title="Intel Ivy Bridge–based Xeon microprocessors">Intel Ivy Bridge–based Xeon microprocessors</a></div>
<p><b>Intel Ivy Bridge–based Xeon microprocessors</b> (also known as <b>Ivy Bridge-E</b>) is the follow-up to <a href="Sandy_Bridge-E" class="mw-redirect" title="Sandy Bridge-E">Sandy Bridge-E</a>, using the same CPU core as the Ivy Bridge processor, but in <a href="LGA_2011" title="LGA 2011">LGA 2011</a>, <a href="LGA_1356" title="LGA 1356">LGA 1356</a> and <a href="LGA_2011-1" class="mw-redirect" title="LGA 2011-1">LGA 2011-1</a> packages for workstations and servers.
</p><p>Additional high-end server processors based on the Ivy Bridge architecture, code named Ivytown, were announced September 10, 2013 at the <a href="Intel_Developer_Forum" title="Intel Developer Forum">Intel Developer Forum</a>, after the usual one year interval between consumer and server product releases.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup>
</p><p>The Ivy Bridge-EP processor line announced in September 2013 has up to 12 cores and 30 MB third level cache, with rumors of Ivy Bridge-EX up to 15 cores and an increased third level cache of up to 37.5 MB,<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-IB-E-legitreviews2_48-0" class="reference"><a href="#cite_note-IB-E-legitreviews2-48"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> although an early leaked lineup of Ivy Bridge-E included processors with a maximum of 6 cores.<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup>
</p><p>Both Core-i7 and Xeon versions are produced: the Xeon versions marketed as <b>Xeon E5-1400 v2</b> act as drop-in replacements for the existing Sandy Bridge-EN based Xeon E5, <b>Xeon E5-2600 V2</b> versions act as drop-in replacements for the existing Sandy Bridge-EP based Xeon E5, while Core-i7 versions designated i7-4820K, i7-4930K and i7-4960X were released on September 10, 2013, remaining compatible with the <a href="Intel_X79" title="Intel X79">X79</a> and <a href="LGA_2011" title="LGA 2011">LGA 2011</a> hardware.<sup id="cite_ref-IB-E-legitreviews2_48-1" class="reference"><a href="#cite_note-IB-E-legitreviews2-48"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-CPU-World-IB-E2_50-0" class="reference"><a href="#cite_note-CPU-World-IB-E2-50"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup>
</p><p>For the intermediate <a href="LGA_1356" title="LGA 1356">LGA 1356</a> socket, Intel launched the <b>Xeon E5-2400 v2</b> (codenamed Ivy Bridge-EN) series in January 2014.<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> These have up to 10 cores.<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup>
</p><p>A new Ivy Bridge-EX line marketed as <b>Xeon E7 v2</b> had no corresponding predecessor using the Sandy Bridge microarchitecture but instead followed the older <a href="Westmere_(microarchitecture)#SERVERDESKTOP" title="Westmere (microarchitecture)">Westmere-EX</a> processors.
</p>
<div class="mw-heading mw-heading2"><h2 id="List_of_Ivy_Bridge_processors">List of Ivy Bridge processors</h2></div>
<p>Processors featuring Intel's HD 4000 graphics (or HD P4000 for Xeon) are set in <b>bold</b>. Other processors feature HD 2500 graphics or HD Graphics unless indicated by N/A.
</p>
<div class="mw-heading mw-heading3"><h3 id="Desktop_processors">Desktop processors</h3></div>
<p>List of announced desktop processors, as follows:
</p>
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<table class="wikitable sortable hover-highlight">
<tbody><tr>
<th colspan="2" rowspan="2">Processor<br>branding<br>and model
</th>
<th rowspan="2">Cores<br>(threads)
</th>
<th colspan="2">CPU <a href="Clock_rate" title="Clock rate">clock rate</a>
</th>
<th colspan="2"><a href="Graphics_processing_unit" title="Graphics processing unit">GPU</a> clock rate
</th>
<th rowspan="2"><a href="L3_cache" class="mw-redirect" title="L3 cache">L3<br>cache</a>
</th>
<th rowspan="2"><a href="Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a>
</th>
<th rowspan="2">Release<br>date
</th>
<th rowspan="2">Release<br>price<br>(USD)
</th>
<th colspan="3">Motherboard
</th></tr>
<tr>
<th>Normal
</th>
<th><a href="Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a>
</th>
<th>Normal
</th>
<th>Turbo
</th>
<th>Socket
</th>
<th>Interface
</th>
<th>Memory
</th></tr>
<tr>
<th style="background-position:center"><br></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center">
</th></tr>
<tr>
<td><a href="Core_i7" class="mw-redirect" title="Core i7">Core i7<br>Extreme</a>
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/77779">4960X</a>
</td>
<td rowspan="2">6 (12)
</td>
<td>3.6 GHz
</td>
<td>4.0 GHz
</td>
<td rowspan="3" colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>15 MB
</td>
<td rowspan="3">130 W
</td>
<td rowspan="3">2013-09-10
</td>
<td>$999<sup id="cite_ref-Ivy_Bridge-E_processors_to_start_at_$310_53-0" class="reference"><a href="#cite_note-Ivy_Bridge-E_processors_to_start_at_$310-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup>
</td>
<td rowspan="3"><a href="LGA_2011" title="LGA 2011">LGA<br>2011</a>
</td>
<td rowspan="25"><a href="Direct_Media_Interface" title="Direct Media Interface">DMI 2.0</a><br><a href="PCI_Express_3.0" class="mw-redirect" title="PCI Express 3.0">PCIe 3.0</a><style data-mw-deduplicate="TemplateStyles:r1041539562">
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</style><sup class="citation nobold" id="ref_desktop-dmi"><a href="#endnote_desktop-dmi">[a]</a></sup>
</td>
<td rowspan="3">Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td rowspan="6"><a href="Core_i7" class="mw-redirect" title="Core i7">Core i7</a>
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/77780">4930K</a>
</td>
<td>3.4 GHz
</td>
<td rowspan="5">3.9 GHz
</td>
<td>12 MB
</td>
<td>$583<sup id="cite_ref-Ivy_Bridge-E_processors_to_start_at_$310_53-1" class="reference"><a href="#cite_note-Ivy_Bridge-E_processors_to_start_at_$310-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup>
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/77781/intel-core-i74820k-processor-10m-cache-up-to-3-90-ghz/specifications.html">4820K</a>
</td>
<td rowspan="5">4 (8)
</td>
<td>3.7 GHz
</td>
<td>10 MB
</td>
<td>$323<sup id="cite_ref-Ivy_Bridge-E_processors_to_start_at_$310_53-2" class="reference"><a href="#cite_note-Ivy_Bridge-E_processors_to_start_at_$310-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup>
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65523">3770K</a></b>
</td>
<td>3.5 GHz
</td>
<td rowspan="16">650 MHz
</td>
<td rowspan="10">1150 MHz
</td>
<td rowspan="4">8 MB
</td>
<td rowspan="2">77 W
</td>
<td rowspan="5">2012-04-23
</td>
<td>$332
</td>
<td rowspan="46"><a href="LGA_1155" title="LGA 1155">LGA<br>1155</a>
</td>
<td rowspan="36">Up to dual<br>channel<br>DDR3-1600<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup>
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65719">3770</a></b>
</td>
<td>3.4 GHz
</td>
<td rowspan="3">$294
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65524">3770S</a></b>
</td>
<td>3.1 GHz
</td>
<td>65 W
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65525">3770T</a></b>
</td>
<td>2.5 GHz
</td>
<td>3.7 GHz
</td>
<td>45 W
</td></tr>
<tr>
<td rowspan="18"><a href="Core_i5" class="mw-redirect" title="Core i5">Core i5</a>
</td>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65520">3570K</a></b>
</td>
<td rowspan="9">4 (4)
</td>
<td rowspan="2">3.4 GHz
</td>
<td rowspan="3">3.8 GHz
</td>
<td rowspan="9">6 MB
</td>
<td rowspan="2">77 W
</td>
<td>$225
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65702">3570</a>
</td>
<td rowspan="3">2012-05-31<sup id="cite_ref-presence-pc_55-0" class="reference"><a href="#cite_note-presence-pc-55"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup>
</td>
<td rowspan="5">$205
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65701">3570S</a>
</td>
<td>3.1 GHz
</td>
<td>65 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65521">3570T</a>
</td>
<td>2.3 GHz
</td>
<td>3.3 GHz
</td>
<td>45 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65516">3550</a>
</td>
<td>3.3 GHz
</td>
<td rowspan="2">3.7 GHz
</td>
<td>77 W
</td>
<td rowspan="2">2012-04-23
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65518">3550S</a>
</td>
<td>3.0 GHz
</td>
<td rowspan="2">65 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65515"><b>3475S</b></a>
</td>
<td>2.9 GHz
</td>
<td rowspan="4">3.6 GHz
</td>
<td rowspan="6">1050 MHz
</td>
<td rowspan="4">2012-05-31<sup id="cite_ref-presence-pc_55-1" class="reference"><a href="#cite_note-presence-pc-55"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup>
</td>
<td>$201
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/68316">3470</a>
</td>
<td>3.2 GHz
</td>
<td>77 W
</td>
<td rowspan="5">$184
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/68315">3470S</a>
</td>
<td rowspan="2">2.9 GHz
</td>
<td>65 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65703">3470T</a>
</td>
<td>2 (4)
</td>
<td>3 MB
</td>
<td>35 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65511">3450</a>
</td>
<td rowspan="8">4 (4)
</td>
<td>3.1 GHz
</td>
<td rowspan="2">3.5 GHz
</td>
<td rowspan="8">6 MB
</td>
<td>77 W
</td>
<td rowspan="2">2012-04-23
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65512">3450S</a>
</td>
<td>2.8 GHz
</td>
<td>65 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/69114">3350P</a>
</td>
<td rowspan="2">3.1 GHz
</td>
<td rowspan="3">3.3 GHz
</td>
<td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>69 W
</td>
<td>2012-09-03
</td>
<td>$177
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76342">3340</a>
</td>
<td rowspan="29">650 MHz
</td>
<td rowspan="29">1050 MHz
</td>
<td>77 W
</td>
<td rowspan="2">2013-09-01
</td>
<td rowspan="2">$182
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76343">3340S</a>
</td>
<td>2.8 GHz
</td>
<td rowspan="3">65 W
</td></tr>
<tr>
<td><b>3335S</b>
</td>
<td rowspan="2">2.7 GHz
</td>
<td rowspan="3">3.2 GHz
</td>
<td rowspan="3">2012-09-03
</td>
<td>$194
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65510">3330S</a>
</td>
<td>$177
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65509">3330</a>
</td>
<td>3.0 GHz
</td>
<td>77 W
</td>
<td>$182
</td></tr>
<tr>
<td rowspan="9"><a href="Core_i3" class="mw-redirect" title="Core i3">Core i3</a>
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74744">3250</a>
</td>
<td rowspan="9">2 (4)
</td>
<td>3.5 GHz
</td>
<td rowspan="24" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="19">3 MB
</td>
<td rowspan="6">55 W
</td>
<td rowspan="2">2013-06-09
</td>
<td>$138
</td>
<td rowspan="24"><a href="Direct_Media_Interface" title="Direct Media Interface">DMI 2.0</a><br><a href="PCI_Express_2" class="mw-redirect" title="PCI Express 2">PCIe 2.0</a>
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20230629210739/https://ark.intel.com/content/www/us/en/ark/products/74746/intel-core-i33245-processor-3m-cache-3-40-ghz.html"><b>3245</b></a>
</td>
<td rowspan="2">3.4 GHz
</td>
<td>$134
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65690">3240</a>
</td>
<td rowspan="3">2012-09-03
</td>
<td>$138
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65692"><b>3225</b></a>
</td>
<td rowspan="2">3.3 GHz
</td>
<td>$134
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65693">3220</a>
</td>
<td rowspan="2">$117
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71053">3210</a>
</td>
<td>3.2 GHz
</td>
<td>2013-01-20
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74745">3250T</a>
</td>
<td>3.0 GHz
</td>
<td rowspan="3">35 W
</td>
<td>2013-06-09
</td>
<td rowspan="2">$138
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/66168">3240T</a>
</td>
<td>2.9 GHz
</td>
<td rowspan="2">2012-09-03
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65694">3220T</a>
</td>
<td>2.8 GHz
</td>
<td>$117
</td></tr>
<tr>
<td rowspan="10">Pentium
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74747">G2140</a>
</td>
<td rowspan="15">2 (2)
</td>
<td>3.3 GHz
</td>
<td rowspan="3">55 W
</td>
<td>2013-06-09
</td>
<td rowspan="3">$86
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71052">G2130</a>
</td>
<td>3.2 GHz
</td>
<td>2013-01-20
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65527">G2120</a>
</td>
<td>3.1 GHz
</td>
<td>2012-09-03
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71097">G2120T</a>
</td>
<td>2.7 GHz
</td>
<td rowspan="2">35 W
</td>
<td>2013-06-09
</td>
<td rowspan="2">$75
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65738">G2100T</a>
</td>
<td>2.6 GHz
</td>
<td>2012-09-03
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74749">G2030</a>
</td>
<td>3.0 GHz
</td>
<td rowspan="3">55 W
</td>
<td>2013-06-09
</td>
<td rowspan="5">$64
</td>
<td rowspan="10">Dual channel<br>DDR3-1333
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71070">G2020</a>
</td>
<td>2.9 GHz
</td>
<td rowspan="2">2013-01-20
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71071">G2010</a>
</td>
<td>2.8 GHz
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74748">G2030T</a>
</td>
<td>2.6 GHz
</td>
<td rowspan="2">35 W
</td>
<td>2013-06-09
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71069">G2020T</a>
</td>
<td>2.5 GHz
</td>
<td>2013-01-20
</td></tr>
<tr>
<td rowspan="5">Celeron
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76344">G1630</a>
</td>
<td>2.8 GHz
</td>
<td rowspan="5">2 MB
</td>
<td rowspan="3">55 W
</td>
<td>2013-09-01
</td>
<td rowspan="2">$52
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71073">G1620</a>
</td>
<td>2.7 GHz
</td>
<td rowspan="2">2013-01-20
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71072">G1610</a>
</td>
<td>2.6 GHz
</td>
<td rowspan="3">$42
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76345">G1620T</a>
</td>
<td>2.4 GHz
</td>
<td rowspan="2">35 W
</td>
<td>2013-09-01
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71074">G1610T</a>
</td>
<td>2.3 GHz
</td>
<td>2013-01-20
</td></tr></tbody></table>
<ol type="a">
<li><span class="citation wikicite" id="endnote_desktop-dmi"><sup></sup></span> Requires a compatible motherboard with 7 series chipsets.
</li></ol>
<p>Suffixes to denote:
</p>
<ul><li>K – Unlocked <span style="color: #969696">(adjustable CPU multiplier up to 63 times)</span></li>
<li>S – Performance-optimized lifestyle <span style="color: #969696">(low power with 65 W TDP)</span></li>
<li>T – Power-optimized lifestyle <span style="color: #969696">(ultra-low power consumption with 35–45 W TDP)</span></li>
<li>P – No on-die video chipset</li>
<li>X – Extreme performance <span style="color: #969696">(adjustable CPU ratio with no ratio limit)</span></li></ul>
<div class="mw-heading mw-heading3"><h3 id="Server_processors">Server processors</h3></div>
<div role="note" class="hatnote navigation-not-searchable">Further information: <a href="Intel_Ivy_Bridge-based_Xeon_microprocessors" class="mw-redirect" title="Intel Ivy Bridge-based Xeon microprocessors">Intel Ivy Bridge-based Xeon microprocessors</a></div>
<table class="wikitable sortable hover-highlight">
<tbody><tr>
<th colspan="2" rowspan="2">Processor<br>branding and model
</th>
<th rowspan="2">Cores<br>(threads)
</th>
<th colspan="2">CPU <a href="Clock_rate" title="Clock rate">clock rate</a>
</th>
<th colspan="2"><a href="Graphics_processing_unit" title="Graphics processing unit">GPU</a> clock rate
</th>
<th rowspan="2"><a href="L3_cache" class="mw-redirect" title="L3 cache">L3<br>cache</a>
</th>
<th rowspan="2"><a href="Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a>
</th>
<th rowspan="2">Release<br>date
</th>
<th rowspan="2">Price<br>(USD)
</th>
<th colspan="3">Motherboard
</th></tr>
<tr>
<th>Normal
</th>
<th><a href="Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a>
</th>
<th>Normal
</th>
<th>Turbo
</th>
<th>Socket
</th>
<th>Interface
</th>
<th>Memory
</th></tr>
<tr>
<th style="background-position:center"><br></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center">
</th></tr>
<tr>
<td rowspan="21">Xeon E7
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75260">8893v2</a>
</td>
<td>6 (12)
</td>
<td>3.4 GHz
</td>
<td rowspan="2">3.7 GHz
</td>
<td rowspan="78" colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="10">37.5 MB
</td>
<td rowspan="6">155 W
</td>
<td rowspan="21">2014-02-18
</td>
<td rowspan="2">$6841
</td>
<td rowspan="21"><a href="LGA_2011-1" class="mw-redirect" title="LGA 2011-1">LGA<br>2011-1</a>
</td>
<td rowspan="21">3× <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a><br>DMI 2.0<br>PCIe 3.0
</td>
<td rowspan="20">Up to quad<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75259">8891v2</a>
</td>
<td>10 (20)
</td>
<td>3.2 GHz
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/79209">8895v2</a>
</td>
<td rowspan="11">15 (30)
</td>
<td rowspan="4">2.8 GHz
</td>
<td>3.6 GHz
</td>
<td>OEM<br>(Oracle)<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup>
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75258">8890v2</a>
</td>
<td rowspan="3">3.4 GHz
</td>
<td>$6841
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75251">4890v2</a>
</td>
<td>$6619
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75242">2890v2</a>
</td>
<td>$6451
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75256">8880Lv2</a>
</td>
<td>2.2 GHz
</td>
<td>2.8 GHz
</td>
<td>105 W
</td>
<td rowspan="2">$5729
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75257">8880v2</a>
</td>
<td rowspan="3">2.5 GHz
</td>
<td rowspan="3">3.1 GHz
</td>
<td rowspan="8">130 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75773">4880v2</a>
</td>
<td>$5506
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75241">2880v2</a>
</td>
<td>$5339
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75255">8870v2</a>
</td>
<td rowspan="3">2.3 GHz
</td>
<td rowspan="3">2.9 GHz
</td>
<td rowspan="5">30 MB
</td>
<td>$4616
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75250">4870v2</a>
</td>
<td>$4394
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75240">2870v2</a>
</td>
<td>$4227
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75254">8857v2</a>
</td>
<td>12 (12)
</td>
<td>3.0 GHz
</td>
<td>3.6 GHz
</td>
<td rowspan="2">$3838
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75249">4860v2</a>
</td>
<td rowspan="4">12 (24)
</td>
<td>2.6 GHz
</td>
<td>3.2 GHz
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75253">8850v2</a>
</td>
<td rowspan="3">2.3 GHz
</td>
<td rowspan="3">2.8 GHz
</td>
<td rowspan="3">24 MB
</td>
<td rowspan="6">105 W
</td>
<td>$3059
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75248">4850v2</a>
</td>
<td>$2837
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75239">2850v2</a>
</td>
<td>$2558
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75247">4830v2</a>
</td>
<td>10 (20)
</td>
<td>2.2 GHz
</td>
<td>2.7 GHz
</td>
<td>20 MB
</td>
<td>$2059
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75246">4820v2</a>
</td>
<td>8 (16)
</td>
<td>2.0 GHz
</td>
<td>2.5 GHz
</td>
<td>16 MB
</td>
<td>$1446
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75245">4809v2</a>
</td>
<td>6 (12)
</td>
<td>1.9 GHz
</td>
<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>12 MB
</td>
<td>$1223
</td>
<td>Up to quad<br>channel<br>DDR3-1333
</td></tr>
<tr>
<td rowspan="53">Xeon E5
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75290">4657Lv2</a>
</td>
<td>12 (24)
</td>
<td rowspan="2">2.4 GHz
</td>
<td rowspan="2">3.2 GHz
</td>
<td>30 MB
</td>
<td>115 W
</td>
<td rowspan="9">2014-03-03
</td>
<td>$4394
</td>
<td rowspan="34"><a href="LGA_2011" title="LGA 2011">LGA<br>2011</a>
</td>
<td rowspan="34">2× <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a><br>DMI 2.0<br>PCIe 3.0
</td>
<td rowspan="5">Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75289">4650v2</a>
</td>
<td rowspan="3">10 (20)
</td>
<td>25 MB
</td>
<td rowspan="2">95 W
</td>
<td>$3616
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75288">4640v2</a>
</td>
<td>2.2 GHz
</td>
<td>2.7 GHz
</td>
<td>20 MB
</td>
<td>$2725
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76350">4624Lv2</a>
</td>
<td>1.9 GHz
</td>
<td>2.5 GHz
</td>
<td>25 MB
</td>
<td>70 W
</td>
<td>$2405
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75287">4627v2</a>
</td>
<td>8 (8)
</td>
<td>3.3 GHz
</td>
<td>3.6 GHz
</td>
<td>16 MB
</td>
<td>130 W
</td>
<td>$2108
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75286">4620v2</a>
</td>
<td rowspan="2">8 (16)
</td>
<td>2.6 GHz
</td>
<td>3.0 GHz
</td>
<td>20 MB
</td>
<td rowspan="4">95 W
</td>
<td>$1611
</td>
<td rowspan="2">Up to quad<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75285">4610v2</a>
</td>
<td>2.3 GHz
</td>
<td>2.7 GHz
</td>
<td>16 MB
</td>
<td>$1219
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75794">4607v2</a>
</td>
<td>6 (12)
</td>
<td>2.6 GHz
</td>
<td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>15 MB
</td>
<td>$885
</td>
<td rowspan="2">Up to quad<br>channel<br>DDR3-1333
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75793">4603v2</a>
</td>
<td>4 (8)
</td>
<td>2.2 GHz
</td>
<td>10 MB
</td>
<td>$551
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75283">2697v2</a>
</td>
<td rowspan="5">12 (24)
</td>
<td>2.7 GHz
</td>
<td>3.5 GHz
</td>
<td rowspan="5">30 MB
</td>
<td>130 W
</td>
<td rowspan="3">2013-09-10
</td>
<td>$2614
</td>
<td rowspan="10">Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td>2696v2
</td>
<td>2.5 GHz
</td>
<td>3.3 GHz
</td>
<td>120 W
</td>
<td>OEM
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75281">2695v2</a>
</td>
<td>2.4 GHz
</td>
<td>3.2 GHz
</td>
<td rowspan="2">115 W
</td>
<td>$2336
</td></tr>
<tr>
<td>2692v2
</td>
<td>2.2 GHz
</td>
<td>3.0 GHz
</td>
<td>June 2013
</td>
<td>OEM<br>(Tianhe-2)
</td></tr>
<tr>
<td>2651v2
</td>
<td>1.8 GHz
</td>
<td>2.2 GHz
</td>
<td>105 W
</td>
<td rowspan="21">2013-09-10
</td>
<td>
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75279">2690v2</a>
</td>
<td rowspan="7">10 (20)
</td>
<td>3.0 GHz
</td>
<td rowspan="2">3.6 GHz
</td>
<td rowspan="9">25 MB
</td>
<td>130 W
</td>
<td>$2057
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75277">2680v2</a>
</td>
<td>2.8 GHz
</td>
<td rowspan="2">115 W
</td>
<td>$1723
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75275">2670v2</a>
</td>
<td>2.5 GHz
</td>
<td>3.3 GHz
</td>
<td>$1552
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75272">2660v2</a>
</td>
<td>2.2 GHz
</td>
<td rowspan="2">3.0 GHz
</td>
<td rowspan="2">95 W
</td>
<td>$1389
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76160">2658v2</a>
</td>
<td>2.4 GHz
</td>
<td>$1750
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75270">2650Lv2</a>
</td>
<td>1.7 GHz
</td>
<td>2.1 GHz
</td>
<td rowspan="2">70 W
</td>
<td>$1219
</td>
<td>Up to quad<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76159">2648Lv2</a>
</td>
<td>1.9 GHz
</td>
<td>2.5 GHz
</td>
<td>$1479
</td>
<td rowspan="4">Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76161">2687Wv2</a>
</td>
<td rowspan="5">8 (16)
</td>
<td>3.4 GHz
</td>
<td rowspan="2">4.0 GHz
</td>
<td>150 W
</td>
<td>$2108
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75273">2667v2</a>
</td>
<td>3.3 GHz
</td>
<td>130 W
</td>
<td>$2057
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75269">2650v2</a>
</td>
<td>2.6 GHz
</td>
<td>3.4 GHz
</td>
<td rowspan="3">20 MB
</td>
<td rowspan="2">95 W
</td>
<td>$1166
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75267">2640v2</a>
</td>
<td>2.0 GHz
</td>
<td>2.5 GHz
</td>
<td>$885
</td>
<td rowspan="2">Up to quad<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76158">2628Lv2</a>
</td>
<td>1.9 GHz
</td>
<td>2.4 GHz
</td>
<td>70 W
</td>
<td>$1216
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75268">2643v2</a>
</td>
<td rowspan="5">6 (12)
</td>
<td>3.5 GHz
</td>
<td>3.8 GHz
</td>
<td>25 MB
</td>
<td>130 W
</td>
<td>$1552
</td>
<td>Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75790">2630v2</a>
</td>
<td>2.6 GHz
</td>
<td>3.1 GHz
</td>
<td rowspan="5">15 MB
</td>
<td>80 W
</td>
<td rowspan="2">$612
</td>
<td rowspan="3">Up to quad<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75791">2630Lv2</a>
</td>
<td>2.4 GHz
</td>
<td>2.8 GHz
</td>
<td>60 W
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75789">2620v2</a>
</td>
<td>2.1 GHz
</td>
<td>2.6 GHz
</td>
<td>80 W
</td>
<td>$406
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75788">2618Lv2</a>
</td>
<td>2.0 GHz
</td>
<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>50 W
</td>
<td>$520
</td>
<td>Up to quad<br>channel<br>DDR3-1333
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75792">2637v2</a>
</td>
<td>4 (8)
</td>
<td>3.5 GHz
</td>
<td>3.8 GHz
</td>
<td>130 W
</td>
<td>$996
</td>
<td>Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75787">2609v2</a>
</td>
<td rowspan="2">4 (4)
</td>
<td>2.5 GHz
</td>
<td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="2">10 MB
</td>
<td rowspan="2">80 W
</td>
<td>$294
</td>
<td rowspan="2">Up to quad<br>channel<br>DDR3-1333
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/76157">2603v2</a>
</td>
<td>1.8 GHz
</td>
<td>$202
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75266">2470v2</a>
</td>
<td rowspan="3">10 (20)
</td>
<td>2.4 GHz
</td>
<td>3.2 GHz
</td>
<td rowspan="3">25 MB
</td>
<td>95 W
</td>
<td rowspan="12">2014-01-09
</td>
<td>$1440
</td>
<td rowspan="12"><a href="LGA_1356" title="LGA 1356">LGA<br>1356</a>
</td>
<td rowspan="12">1× <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a><br>DMI 2.0<br>PCIe 3.0
</td>
<td rowspan="9">Up to triple<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75973">2448Lv2</a>
</td>
<td>1.8 GHz
</td>
<td>2.4 GHz
</td>
<td>70 W
</td>
<td>$1424
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75265">2450Lv2</a>
</td>
<td>1.7 GHz
</td>
<td>2.1 GHz
</td>
<td>60 W
</td>
<td>$1219
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75264">2450v2</a>
</td>
<td rowspan="3">8 (16)
</td>
<td>2.5 GHz
</td>
<td>3.3 GHz
</td>
<td rowspan="3">20 MB
</td>
<td rowspan="2">95 W
</td>
<td>$1107
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75263">2440v2</a>
</td>
<td>1.9 GHz
</td>
<td>2.4 GHz
</td>
<td>$832
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75974">2428Lv2</a>
</td>
<td>1.8 GHz
</td>
<td>2.3 GHz
</td>
<td>60 W
</td>
<td>$1013
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75785">2430v2</a>
</td>
<td rowspan="4">6 (12)
</td>
<td>2.5 GHz
</td>
<td>3.0 GHz
</td>
<td rowspan="4">15 MB
</td>
<td rowspan="2">80 W
</td>
<td>$551
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75784">2420v2</a>
</td>
<td>2.2 GHz
</td>
<td>2.7 GHz
</td>
<td>$406
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75786">2430Lv2</a>
</td>
<td>2.4 GHz
</td>
<td>2.8 GHz
</td>
<td>60 W
</td>
<td>$612
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75783">2418Lv2</a>
</td>
<td>2.0 GHz
</td>
<td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>50 W
</td>
<td>$607
</td>
<td rowspan="3">Up to triple<br>channel<br>DDR3-1333
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75782">2407v2</a>
</td>
<td rowspan="2">4 (4)
</td>
<td>2.4 GHz
</td>
<td rowspan="2">10 MB
</td>
<td rowspan="2">80 W
</td>
<td>$250
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75975">2403v2</a>
</td>
<td>1.8 GHz
</td>
<td>$192
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/77912">1680v2</a>
</td>
<td>8 (16)
</td>
<td>3.0 GHz
</td>
<td>3.9 GHz
</td>
<td>25 MB
</td>
<td rowspan="5">130 W
</td>
<td rowspan="5">2013-09-10
</td>
<td>$1723
</td>
<td rowspan="5"><a href="LGA_2011" title="LGA 2011">LGA<br>2011</a>
</td>
<td rowspan="9">0× <a href="Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a><br>DMI 2.0<br>PCIe 3.0
</td>
<td rowspan="4">Up to quad<br>channel<br>DDR3-1866
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75781">1660v2</a>
</td>
<td rowspan="2">6 (12)
</td>
<td>3.7 GHz
</td>
<td>4.0 GHz
</td>
<td>15 MB
</td>
<td>$1080
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75780">1650v2</a>
</td>
<td>3.5 GHz
</td>
<td rowspan="2">3.9 GHz
</td>
<td>12 MB
</td>
<td>$583
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75779">1620v2</a>
</td>
<td>4 (8)
</td>
<td>3.7 GHz
</td>
<td rowspan="2">10 MB
</td>
<td>$294
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/77785">1607v2</a>
</td>
<td>4 (4)
</td>
<td>3.0 GHz
</td>
<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>$244
</td>
<td>Up to quad<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75778">1428Lv2</a>
</td>
<td>6 (12)
</td>
<td>2.2 GHz
</td>
<td>2.7 GHz
</td>
<td>15 MB
</td>
<td>60 W
</td>
<td rowspan="4">2014-01-09
</td>
<td>$494
</td>
<td rowspan="4"><a href="LGA_1356" title="LGA 1356">LGA<br>1356</a>
</td>
<td rowspan="4">Up to triple<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75777">1410v2</a>
</td>
<td>4 (8)
</td>
<td>2.8 GHz
</td>
<td>3.2 GHz
</td>
<td>10 MB
</td>
<td rowspan="2">80 W
</td>
<td rowspan="2">OEM
</td></tr>
<tr>
<td rowspan="2">Pentium
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/77919">1403v2</a>
</td>
<td rowspan="2">2 (2)
</td>
<td>2.6 GHz
</td>
<td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="2">6 MB
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/77918">1405v2</a>
</td>
<td>1.4 GHz
</td>
<td>40 W
</td>
<td>$156
</td></tr>
<tr>
<td rowspan="14">Xeon E3
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65722">1290v2</a>
</td>
<td rowspan="8">4 (8)
</td>
<td>3.7 GHz
</td>
<td>4.1 GHz
</td>
<td rowspan="10">8 MB
</td>
<td>87 W
</td>
<td rowspan="11">2012-05-14
</td>
<td>$885
</td>
<td rowspan="11"><a href="LGA_1155" title="LGA 1155">LGA<br>1155</a>
</td>
<td rowspan="14"><a href="Direct_Media_Interface" title="Direct Media Interface">DMI 2.0</a><br><a href="PCI_Express_3.0" class="mw-redirect" title="PCI Express 3.0">PCIe 3.0</a>
</td>
<td rowspan="14">Up to dual<br>channel<br>DDR3-1600
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65725">1280v2</a>
</td>
<td>3.6 GHz
</td>
<td>4.0 GHz
</td>
<td>69 W
</td>
<td>$623
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65726"><b>1275v2</b></a>
</td>
<td rowspan="2">3.5 GHz
</td>
<td rowspan="2">3.9 GHz
</td>
<td>650 MHz
</td>
<td>1.25 GHz
</td>
<td>77 W
</td>
<td>$350
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65727">1270v2</a>
</td>
<td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>69 W
</td>
<td>$339
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65728">1265Lv2</a>
</td>
<td>2.5 GHz
</td>
<td>3.5 GHz
</td>
<td>650 MHz
</td>
<td>1.15 GHz
</td>
<td>45 W
</td>
<td>$305
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65729"><b>1245v2</b></a>
</td>
<td rowspan="2">3.4 GHz
</td>
<td rowspan="2">3.8 GHz
</td>
<td>650 MHz
</td>
<td>1.25 GHz
</td>
<td>77 W
</td>
<td>$273
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65730">1240v2</a>
</td>
<td colspan="2" rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="2">69 W
</td>
<td>$261
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65732">1230v2</a>
</td>
<td>3.3 GHz
</td>
<td>3.7 GHz
</td>
<td>$230
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65733"><b>1225v2</b></a>
</td>
<td rowspan="2">4 (4)
</td>
<td>3.2 GHz
</td>
<td>3.6 GHz
</td>
<td>650 MHz
</td>
<td>1.25 GHz
</td>
<td>77 W
</td>
<td>$224
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65734">1220v2</a>
</td>
<td>3.1 GHz
</td>
<td rowspan="2">3.5 GHz
</td>
<td colspan="2" rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>69 W
</td>
<td>$203
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65735">1220Lv2</a>
</td>
<td>2 (4)
</td>
<td>2.3 GHz
</td>
<td>3 MB
</td>
<td>17 W
</td>
<td>$189
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/78519">1135Cv2</a>
</td>
<td rowspan="3">4 (8)
</td>
<td>3.0 GHz
</td>
<td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="3">8 MB
</td>
<td>55 W
</td>
<td rowspan="3">2013-09-10
</td>
<td>OEM
</td>
<td rowspan="3">BGA<br>1284
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/78168">1125Cv2</a>
</td>
<td>2.5 GHz
</td>
<td>40 W
</td>
<td>$448
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/78167">1105Cv2</a>
</td>
<td>1.8 GHz
</td>
<td>25 W
</td>
<td>$320
</td></tr></tbody></table>
<p>Suffixes to denote:
</p>
<ul><li>L – Low power</li>
<li>C – Embedded applications</li>
<li>W – Optimized for workstations</li></ul>
<div class="mw-heading mw-heading3"><h3 id="Mobile_processors">Mobile processors</h3></div>
<table class="wikitable sortable hover-highlight">
<tbody><tr>
<th colspan="2" rowspan="2">Processor<br>branding and model
</th>
<th rowspan="2">Cores<br>(threads)
</th>
<th colspan="4">Programmable TDP
</th>
<th>CPU Turbo
</th>
<th colspan="2"><a href="Graphics_processing_unit" title="Graphics processing unit">GPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a>
</th>
<th rowspan="2"><a href="L3_cache" class="mw-redirect" title="L3 cache">L3<br>cache</a>
</th>
<th rowspan="2">Release<br>date
</th>
<th rowspan="2">Price<br>(USD)
</th></tr>
<tr>
<th>SDP<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup>
</th>
<th>cTDP down
</th>
<th>Nominal TDP
</th>
<th>cTDP up
</th>
<th>1-core
</th>
<th>Normal
</th>
<th>Turbo
</th></tr>
<tr>
<th style="background-position:center"><br></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center"></th>
<th style="background-position:center">
</th></tr>
<tr>
<td rowspan="2">Core i7<br>Extreme
</td>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71096">3940XM</a></b>
</td>
<td rowspan="12">4 (8)
</td>
<td rowspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>45 W / ? GHz
</td>
<td>55 W / 3.0 GHz
</td>
<td>65 W / ? GHz
</td>
<td>3.9 GHz
</td>
<td rowspan="12">650 MHz
</td>
<td>1350 MHz
</td>
<td rowspan="4">8 MB
</td>
<td>2012-09-30
</td>
<td rowspan="2">$1096
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64887">3920XM</a></b>
</td>
<td>45 W / ? GHz
</td>
<td>55 W / 2.9 GHz
</td>
<td>65 W / ? GHz
</td>
<td rowspan="2">3.8 GHz
</td>
<td rowspan="2">1300 MHz
</td>
<td>2012-04-23
</td></tr>
<tr>
<td rowspan="20"><a href="List_of_Intel_Core_i7_microprocessors" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7</a>
</td>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/70846">3840QM</a></b>
</td>
<td rowspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>45 W / 2.8 GHz
</td>
<td rowspan="11" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>2012-09-30
</td>
<td rowspan="2">$568
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64889">3820QM</a></b>
</td>
<td rowspan="2">45 W / 2.7 GHz
</td>
<td rowspan="2">3.7 GHz
</td>
<td>1250 MHz
</td>
<td>2012-04-23
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/70847">3740QM</a></b>
</td>
<td>1300 MHz
</td>
<td rowspan="8">6 MB
</td>
<td>2012-09-30
</td>
<td rowspan="2">$378
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64891">3720QM</a></b>
</td>
<td>45 W / 2.6 GHz
</td>
<td>3.6 GHz
</td>
<td>1250 MHz
</td>
<td>2012-04-23
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71460">3635QM</a></b>
</td>
<td>45 W / 2.4 GHz
</td>
<td>3.4 GHz
</td>
<td>1200 MHz
</td>
<td rowspan="3">2012-09-30
</td>
<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71458">3632QM</a></b>
</td>
<td>35 W / 2.2 GHz
</td>
<td>3.2 GHz
</td>
<td rowspan="2">1150 MHz
</td>
<td rowspan="5">$378
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71459">3630QM</a></b>
</td>
<td>45 W / 2.4 GHz
</td>
<td>3.4 GHz
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64900">3615QM</a></b>
</td>
<td>45 W / 2.3 GHz
</td>
<td>3.3 GHz
</td>
<td>1200 MHz
</td>
<td rowspan="3">2012-04-23
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64901">3612QM</a></b>
</td>
<td>35 W / 2.1 GHz
</td>
<td>3.1 GHz
</td>
<td rowspan="2">1100 MHz
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64899">3610QM</a></b>
</td>
<td>45 W / 2.3 GHz
</td>
<td>3.3 GHz
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72015">3689Y</a></b>
</td>
<td rowspan="34">2 (4)
</td>
<td>7 W / ? GHz
</td>
<td>10 W / ? GHz
</td>
<td>13 W / 1.5 GHz
</td>
<td>2.6 GHz
</td>
<td rowspan="4">350 MHz
</td>
<td>850 MHz
</td>
<td rowspan="10">4 MB
</td>
<td>2013-01-07
</td>
<td>$362
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71258">3687U</a></b>
</td>
<td rowspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 2.1 GHz
</td>
<td>25 W / 3.1 GHz
</td>
<td>3.3 GHz
</td>
<td>1200 MHz
</td>
<td>2013-01-20
</td>
<td rowspan="3">$346
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64898">3667U</a></b>
</td>
<td>14 W / ? GHz
</td>
<td rowspan="2">17 W / 2.0 GHz
</td>
<td>25 W / 3.0 GHz
</td>
<td>3.2 GHz
</td>
<td>1150 MHz
</td>
<td>2012-06-03
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72054">3537U</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>25 W / 2.9 GHz
</td>
<td>3.1 GHz
</td>
<td>1200 MHz
</td>
<td>2013-01-20
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65712">3555LE</a></b>
</td>
<td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>25 W / 2.5 GHz
</td>
<td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>3.2 GHz
</td>
<td>550 MHz
</td>
<td>1000 MHz
</td>
<td>2012-06-03
</td>
<td>$360
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71255">3540M</a></b>
</td>
<td>35 W / 3.0 GHz
</td>
<td>3.7 GHz
</td>
<td rowspan="3">650 MHz
</td>
<td>1300 MHz
</td>
<td>2013-01-20
</td>
<td>$346
</td></tr>
<tr>
<td><b>3525M</b>
</td>
<td rowspan="2">35 W / 2.9 GHz
</td>
<td rowspan="2">3.6 GHz
</td>
<td>1350 MHz
</td>
<td>Q3 2012
</td>
<td>
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64893">3520M</a></b>
</td>
<td>1250 MHz
</td>
<td rowspan="4">2012-06-03
</td>
<td rowspan="2">$346
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65714">3517U</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.9 GHz
</td>
<td>25 W / 2.8 GHz
</td>
<td>3.0 GHz
</td>
<td rowspan="2">350 MHz
</td>
<td>1150 MHz
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65713">3517UE</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.7 GHz
</td>
<td>25 W / 2.6 GHz
</td>
<td>2.8 GHz
</td>
<td>1000 MHz
</td>
<td>$330
</td></tr>
<tr>
<td rowspan="14"><a href="Core_i5-3427U" class="mw-redirect" title="Core i5-3427U">Core i5</a>
</td>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65704">3610ME</a></b>
</td>
<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>35 W / 2.7 GHz
</td>
<td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>3.3 GHz
</td>
<td>650 MHz
</td>
<td>950 MHz
</td>
<td rowspan="22">3 MB
</td>
<td>$276
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72014">3439Y</a></b>
</td>
<td>7 W / ? GHz
</td>
<td>10 W / ? GHz
</td>
<td>13 W / 1.5 GHz
</td>
<td>2.3 GHz
</td>
<td>350 MHz
</td>
<td>850 MHz
</td>
<td>2013-01-07
</td>
<td>$250
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71259">3437U</a></b>
</td>
<td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.9 GHz
</td>
<td>25 W / 2.4 GHz
</td>
<td>2.9 GHz
</td>
<td>650 MHz
</td>
<td>1200 MHz
</td>
<td>2013-01-20
</td>
<td rowspan="2">$225
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64903">3427U</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.8 GHz
</td>
<td>25 W / 2.3 GHz
</td>
<td>2.8 GHz
</td>
<td>350 MHz
</td>
<td>1150 MHz
</td>
<td>2012-06-03
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71256">3380M</a></b>
</td>
<td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>35 W / 2.9 GHz
</td>
<td rowspan="36" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>3.6 GHz
</td>
<td rowspan="4">650 MHz
</td>
<td>1250 MHz
</td>
<td>2013-01-20
</td>
<td>$266
</td></tr>
<tr>
<td><b>3365M</b>
</td>
<td rowspan="2">35 W / 2.8 GHz
</td>
<td rowspan="2">3.5 GHz
</td>
<td>1350 MHz
</td>
<td>Q3 2012
</td>
<td>
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64895">3360M</a></b>
</td>
<td>1200 MHz
</td>
<td>2012-06-03
</td>
<td>$266
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71257">3340M</a></b>
</td>
<td>35 W / 2.7 GHz
</td>
<td>3.4 GHz
</td>
<td>1250 MHz
</td>
<td>2013-01-20
</td>
<td>$225
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72013">3339Y</a></b>
</td>
<td>7 W / ? GHz
</td>
<td>10 W / ? GHz
</td>
<td>13 W / 1.5 GHz
</td>
<td>2.0 GHz
</td>
<td>350 MHz
</td>
<td>850 MHz
</td>
<td>2013-01-07
</td>
<td>$250
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72055">3337U</a></b>
</td>
<td rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.8 GHz
</td>
<td>2.7 GHz
</td>
<td>350 MHz
</td>
<td>1100 MHz
</td>
<td>2013-01-20
</td>
<td rowspan="5">$225
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/64896">3320M</a></b>
</td>
<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>35 W / 2.6 GHz
</td>
<td>3.3 GHz
</td>
<td>650 MHz
</td>
<td>1200 MHz
</td>
<td rowspan="2">2012-06-03
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65707">3317U</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.7 GHz
</td>
<td>2.6 GHz
</td>
<td>350 MHz
</td>
<td>1050 MHz
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72164">3230M</a></b>
</td>
<td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>35 W / 2.6 GHz
</td>
<td>3.2 GHz
</td>
<td rowspan="2">650 MHz
</td>
<td rowspan="2">1100 MHz
</td>
<td>2013-01-20
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/67355">3210M</a></b>
</td>
<td>35 W / 2.5 GHz
</td>
<td>3.1 GHz
</td>
<td>2012-06-03
</td></tr>
<tr>
<td rowspan="9"><a href="List_of_Intel_Core_i3_microprocessors" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3</a>
</td>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72012">3229Y</a></b>
</td>
<td>7 W / ? GHz
</td>
<td>10 W / ? GHz
</td>
<td>13 W / 1.4 GHz
</td>
<td rowspan="26" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="4">350 MHz
</td>
<td>850 MHz
</td>
<td>2013-01-07
</td>
<td>$250
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72057">3227U</a></b>
</td>
<td rowspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.9 GHz
</td>
<td>1100 MHz
</td>
<td>2013-01-20
</td>
<td rowspan="2">$225
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65697">3217U</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.8 GHz
</td>
<td>1050 MHz
</td>
<td>2012-06-24
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65696">3217UE</a></b>
</td>
<td>14 W / ? GHz
</td>
<td>17 W / 1.6 GHz
</td>
<td>900 MHz
</td>
<td>July 2013
</td>
<td>$261
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72058">3130M</a></b>
</td>
<td rowspan="22" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>35 W / 2.6 GHz
</td>
<td rowspan="4">650 MHz
</td>
<td rowspan="2">1100 MHz
</td>
<td>2013-01-20
</td>
<td rowspan="4">$225
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71465">3120M</a></b>
</td>
<td>35 W / 2.5 GHz
</td>
<td>2012-09-30
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65698">3120ME</a></b>
</td>
<td rowspan="2">35 W / 2.4 GHz
</td>
<td>900 MHz
</td>
<td>July 2013
</td></tr>
<tr>
<td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65700">3110M</a></b>
</td>
<td>1000 MHz
</td>
<td>2012-06-24
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/78170">3115C</a>
</td>
<td>25 W / 2.5 GHz
</td>
<td rowspan="2" colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td rowspan="2">4 MB
</td>
<td rowspan="2">2013-09-10
</td>
<td>$241
</td></tr>
<tr>
<td rowspan="7">Pentium
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/78169">B925C</a>
</td>
<td>15 W / 2.0 GHz
</td>
<td>OEM
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/78429">A1018</a>
</td>
<td rowspan="15">2 (2)
</td>
<td>35 W / 2.1 GHz
</td>
<td rowspan="3">650 MHz
</td>
<td>1000 MHz
</td>
<td>1 MB
</td>
<td>June 2013
</td>
<td>$86 (India)
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72059">2030M</a>
</td>
<td>35 W / 2.5 GHz
</td>
<td rowspan="3">1100 MHz
</td>
<td rowspan="14">2 MB
</td>
<td>2013-01-20
</td>
<td rowspan="4">$134
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71142">2020M</a>
</td>
<td>35 W / 2.4 GHz
</td>
<td>2012-09-30
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75191">2127U</a>
</td>
<td>17 W / 1.9 GHz
</td>
<td rowspan="4">350 MHz
</td>
<td>2013-06-09
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71469">2117U</a>
</td>
<td>17 W / 1.8 GHz
</td>
<td>1000 MHz
</td>
<td>2012-09-30
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72016">2129Y</a>
</td>
<td>7 W
</td>
<td>10 W / 1.1 GHz
</td>
<td>850 MHz
</td>
<td>2013-01-07
</td>
<td>$150
</td></tr>
<tr>
<td rowspan="10">Celeron
</td>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75102">1019Y</a>
</td>
<td>7 W
</td>
<td>10 W / 1.0 GHz
</td>
<td>800 MHz
</td>
<td>April 2013
</td>
<td>$153
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74344">1020E</a>
</td>
<td rowspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—
</td>
<td>35 W / 2.2 GHz
</td>
<td rowspan="4">650 MHz
</td>
<td rowspan="7">1000 MHz
</td>
<td rowspan="2">2013-01-20
</td>
<td rowspan="7">$86
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71994">1020M</a>
</td>
<td>35 W / 2.1 GHz
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75193">1005M</a>
</td>
<td>35 W / 1.9 GHz
</td>
<td>2013-06-09
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72060">1000M</a>
</td>
<td>35 W / 1.8 GHz
</td>
<td rowspan="2">2013-01-20
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/71995">1037U</a>
</td>
<td>17 W / 1.8 GHz
</td>
<td rowspan="5">350 MHz
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/75192">1017U</a>
</td>
<td>17 W / 1.6 GHz
</td>
<td>2013-06-09
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/72061">1007U</a>
</td>
<td>17 W / 1.5 GHz
</td>
<td rowspan="3">2013-01-20
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74345">1047UE</a>
</td>
<td>17 W / 1.4 GHz
</td>
<td rowspan="2">900 MHz
</td>
<td>$134
</td></tr>
<tr>
<td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/74346">927UE</a>
</td>
<td>1 (1)
</td>
<td>17 W / 1.5 GHz
</td>
<td>1 MB
</td>
<td>$107
</td></tr></tbody></table>
<p>Suffixes to denote:
</p>
<ul><li>Y – <b>Fanless Ultrabook:</b> Dual-core extreme ultra-low power (TDP 13 W, SDP 7 W)</li>
<li>U – <b>Fanned Ultrabook:</b> Dual-core ultra-low power (TDP 17 W)</li>
<li>C – Communications</li>
<li>M – Dual-core</li>
<li>QM – Quad-core</li>
<li>XM – Quad-core extreme performance <span style="color: #969696">(adjustable CPU ratio with no ratio limit)</span></li>
<li>ME – Dual-core embedded</li></ul>
<div class="mw-heading mw-heading2"><h2 id="Roadmap">Roadmap</h2></div>
<p>Intel demonstrated the <a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> architecture in September 2011, which began release in 2013 as the successor to <a href="Sandy_Bridge_(microarchitecture)" class="mw-redirect" title="Sandy Bridge (microarchitecture)">Sandy Bridge</a> and Ivy Bridge.<sup id="cite_ref-haswell_58-0" class="reference"><a href="#cite_note-haswell-58"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="Fixes">Fixes</h2></div>
<p>Microsoft has released a microcode update for selected Sandy Bridge and Ivy Bridge CPUs for Windows 7 and up that addresses stability issues. The update, however, negatively impacts Intel <a href="List_of_Haswell_processors" class="mw-redirect" title="List of Haswell processors">G3258</a> and <a href="List_of_Intel_Core_i3_microprocessors" class="mw-redirect" title="List of Intel Core i3 microprocessors">4010U</a> CPU models.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div>
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<ul><li><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">List of Intel CPU microarchitectures</a></li></ul>
<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>
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</style><div class="reflist reflist-lower-alpha">
<div class="mw-references-wrap"><ol class="references">
<li id="cite_note-transistor-counts-40"><span class="mw-cite-backlink">^ <a href="#cite_ref-transistor-counts_40-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-transistor-counts_40-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-transistor-counts_40-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text">Transistor counts for M-2, H-2 and HM-4 were determined by a comparison of transistor counts in Sandy Bridge and HE-4. Performing a comparative analysis gave counts of 108 million transistors per core, 67 million transistors per 1 MB of L3 cache, 88 million transistors for the memory controller and other chip features, and roughly 21 million transistors for each execution unit inside the Intel HD 4000. All this is an attempt to determine the transistor count mathematically, and is not backed by any sources. Thus, these transistor counts may be inaccurate.</span>
</li>
</ol></div></div>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
<div class="reflist reflist-columns references-column-width" style="column-width: 30em;">
<ol class="references">
<li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">
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/* end https://en.wikipedia.org/ */
</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140116133839/http://www.intelfreepress.com/news/origin-of-a-codename-ivy-bridge/48">"Origin of a Codename: Ivy Bridge"</a>. <i>Intel Free Press</i>. 19 April 2012. Archived from <a rel="nofollow" class="external text" href="http://www.intelfreepress.com/news/origin-of-a-codename-ivy-bridge/48">the original</a> on 16 January 2014<span class="reference-accessdate">. Retrieved <span class="nowrap">16 January</span> 2014</span>.</cite></span>
</li>
<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.techpowerup.com/153756/Ivy-Bridge-Quad-Core-to-Have-77W-TDP-Intel-Plans-for-LGA1155-Ivy-Bridge-Entry.html">"Ivy Bridge Quad-Core to Have 77W TDP, Intel Plans for LGA1155 Ivy Bridge Entry"</a>. <i>techPowerUp</i>. October 18, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><cite id="CITEREFAnand_Lal_Shimpi2011" class="citation news cs1">Anand Lal Shimpi (June 1, 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110603061951/http://www.anandtech.com/show/4406/correction-ivy-bridge-and-thunderbolt-featured-not-integrated">"Correction: Ivy Bridge and Thunderbolt – Featured, not Integrated"</a>. <i><a href="AnandTech" title="AnandTech">AnandTech</a></i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4406/correction-ivy-bridge-and-thunderbolt-featured-not-integrated/">the original</a> on June 3, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">November 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite id="CITEREFGruener2011" class="citation news cs1">Gruener, Wolfgang (October 19, 2011). <a rel="nofollow" class="external text" href="http://www.tomshardware.com/news/ivy-bridge-processor-release-22nm-3d-transistor,13753.html">"Intel to Sell Ivy Bridge Late in Q4 2011"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><cite id="CITEREFDemerjian2012" class="citation web cs1">Demerjian, Charlie (April 23, 2012). <a rel="nofollow" class="external text" href="http://www.semiaccurate.com/2012/04/23/intel-launches-ivy-bridge-amid-crushing-marketing-buzzwords/">"Intel launches Ivy Bridge amid crushing marketing buzzwords"</a>. <i>SemiAccurate</i><span class="reference-accessdate">. Retrieved <span class="nowrap">September 6,</span> 2024</span>.</cite></span>
</li>
<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><cite id="CITEREFWalton2012" class="citation web cs1">Walton, Jarred (September 7, 2012). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120909170222/http://www.anandtech.com/show/6249/intels-pentium-and-core-i3-desktop-ivy-bridge-cpus-arrive">"Intel's Pentium and Core i3 Desktop Ivy Bridge CPUs Arrive"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/6249/intels-pentium-and-core-i3-desktop-ivy-bridge-cpus-arrive">the original</a> on September 9, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/support/articles/000006105/processors.html">"Does My Intel® Processor Support Microsoft Windows® 10?"</a>. <i>Intel</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 21,</span> 2019</span>.</cite></span>
</li>
<li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/cd/corporate/europe/emea/heb/290083.htm">"Intel Israel: Innovation as a Leadership Strategy"</a>. <i>Intel</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 6,</span> 2014</span>.</cite></span>
</li>
<li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><cite id="CITEREFWebster2011" class="citation web cs1">Webster, Clive (October 10, 2011). <a rel="nofollow" class="external text" href="http://www.bit-tech.net/hardware/cpus/2011/10/10/all-about-ivy-bridge/6">"Ivy Bridge Media Upgrades and Security Features"</a>. <i>Bit-Tech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">December 22,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><cite id="CITEREFShvets2011" class="citation web cs1">Shvets, Gennadiy (November 27, 2011). <a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2011/2011112701_Ivy_Bridge_desktop_CPU_lineup_details.html">"Ivy Bridge desktop CPU lineup details"</a>. <i>CPU-World</i><span class="reference-accessdate">. Retrieved <span class="nowrap">December 22,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors-using-new-3-d-structure">"Intel Reinvents Transistors Using New 3-D structure"</a>. <i>Intel Newsroom</i>. May 4, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">May 4,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-ieee_spectrum-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-ieee_spectrum_12-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFTaylorCox2011" class="citation web cs1">Taylor, Greg; Cox, George (September 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190701135731/https://spectrum.ieee.org/computing/hardware/behind-intels-new-randomnumber-generator/0">"Behind Intel's New Random-Number Generator"</a>. <i>Spectrum</i>. <a href="IEEE" class="mw-redirect" title="IEEE">IEEE</a>. Archived from <a rel="nofollow" class="external text" href="https://spectrum.ieee.org/computing/hardware/behind-intels-new-randomnumber-generator/0">the original</a> on July 1, 2019<span class="reference-accessdate">. Retrieved <span class="nowrap">December 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-bull_mountain-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-bull_mountain_13-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://software.intel.com/en-us/articles/download-the-latest-bull-mountain-software-implementation-guide/?wapkw=%28bull+mountain%29">"Bull Mountain Software Implementation Guide"</a>. <i>Intel</i>. June 12, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 4,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://blogs.msdn.microsoft.com/chuckw/2012/09/11/directxmath-f16c-and-fma/">"DirectXMath: F16C and FMA"</a>. <i>Microsoft</i><span class="reference-accessdate">. Retrieved <span class="nowrap">March 21,</span> 2018</span>.</cite></span>
</li>
<li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text"><cite id="CITEREFHamburg2012" class="citation web cs1">Hamburg, Michael (December 11, 2012). <a rel="nofollow" class="external text" href="http://electronicdesign.com/learning-resources/understanding-intels-ivy-bridge-random-number-generator">"Understanding Intel's Ivy Bridge Random Number Generator"</a>. <i>Electronic Design</i><span class="reference-accessdate">. Retrieved <span class="nowrap">March 21,</span> 2018</span>.</cite></span>
</li>
<li id="cite_note-IB-16"><span class="mw-cite-backlink">^ <a href="#cite_ref-IB_16-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-IB_16-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFShimpi2011" class="citation web cs1">Shimpi, Anand Lal (September 13, 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110923181345/http://www.anandtech.com/show/4790/ivy-bridge-overclocking-ratio-changes-without-reboot-more-ratios-and-ddr32800">"Ivy Bridge Overclocking: Ratio Changes Without Reboot, More Ratios and DDR3-2800"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4790/ivy-bridge-overclocking-ratio-changes-without-reboot-more-ratios-and-ddr32800">the original</a> on September 23, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">February 21,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text"><cite id="CITEREFKarmehed2011" class="citation web cs1">Karmehed, Anton (May 31, 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120525101003/http://www.nordichardware.com/news/69-cpu-chipset/43332-intel-ivy-bridge-gets-variable-tdp-and-thunderbolt.html">"Intel Ivy Bridge gets variable TDP and Thunderbolt"</a>. <i>NHW</i>. Archived from <a rel="nofollow" class="external text" href="http://www.nordichardware.com/news/69-cpu-chipset/43332-intel-ivy-bridge-gets-variable-tdp-and-thunderbolt.html">the original</a> on May 25, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">December 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><cite id="CITEREFShimpi2012" class="citation web cs1">Shimpi, Anand Lal (October 5, 2012). <a rel="nofollow" class="external text" href="https://archive.today/20130628103529/http://www.anandtech.com/show/6355/intels-haswell-architecture/6">"Intel's Haswell Architecture Analyzed"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/6355/intels-haswell-architecture/6">the original</a> on June 28, 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">October 20,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://community.intel.com/t5/Processors/Supervisory-Mode-Execution-Prevention-SMEP-on-all-IVY-Bridge/td-p/201889">"Supervisory Mode Execution Prevention (SMEP) on all IVY Bridge processors?"</a>. <i>Intel Community</i>. October 10, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">September 25,</span> 2024</span>.</cite></span>
</li>
<li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.phoronix.com/news/Linux-Patch-AMD-CPUID-Faulting">"AMD Preps Linux Support For User CPUID Faulting"</a>. <i>www.phoronix.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">June 9,</span> 2025</span>.</cite></span>
</li>
<li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html">"Intel 64 and IA-32 Architectures Optimization Reference Manual"</a>. <i>Intel</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/Assets/en_US/PDF/manual/248966.pdf?wapkw=order+number+248966-025">"Intel 64 and IA-32 Architectures Optimization Reference Manual"</a> <span class="cs1-format">(PDF)</span>. <i>Intel</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-anandtech_ivy_bridge-23"><span class="mw-cite-backlink">^ <a href="#cite_ref-anandtech_ivy_bridge_23-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-anandtech_ivy_bridge_23-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFVättö2011" class="citation web cs1">Vättö, Kristian (May 6, 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110509021933/http://www.anandtech.com/show/4318/intel-roadmap-ivy-bridge-panther-point-ssds">"Intel's Roadmap: Ivy Bridge, Panther Point, and SSDs"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4318/intel-roadmap-ivy-bridge-panther-point-ssds/">the original</a> on May 9, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">November 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://downloadmirror.intel.com/29969/eng/ReleaseNotes_15.33.53.5161.pdf">"Release Notes Driver Version: 15.33.53.5161"</a> <span class="cs1-format">(PDF)</span>. <i>intel</i>. October 23, 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></span>
</li>
<li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><cite id="CITEREFLarabel2017" class="citation web cs1">Larabel, Michael (April 14, 2017). <a rel="nofollow" class="external text" href="https://www.phoronix.com/scan.php?page=news_item&px=Intel-IVB-GL42-Mesa-17.1">"Intel Ivy Bridge Gets OpenGL 4.2 on Mesa 17.1"</a>. <i>Phoronix</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2017</span>.</cite></span>
</li>
<li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><cite id="CITEREFNilsson2012" class="citation web cs1">Nilsson, LG (March 31, 2012). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121017150543/http://vr-zone.com/articles/most-desktop-ivy-bridge-systems-won-t-support-three-displays/15407.html">"Most desktop Ivy Bridge systems won't support three displays"</a>. <i>VR-Zone</i>. Archived from <a rel="nofollow" class="external text" href="http://vr-zone.com/articles/most-desktop-ivy-bridge-systems-won-t-support-three-displays/15407.html">the original</a> on October 17, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">October 17,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><cite id="CITEREFDelahunty2011" class="citation web cs1">Delahunty, James (March 30, 2011). <a rel="nofollow" class="external text" href="http://www.afterdawn.com/news/article.cfm/2011/03/30/intel_ivy_bridge_chips_feature_pci_express_3_0">"Intel Ivy Bridge chips feature PCI Express 3.0"</a>. <i>After Dawn News</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text"><cite id="CITEREFAngelini2013" class="citation web cs1">Angelini, Chris (September 3, 2013). <a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/core-i7-4960x-ivy-bridge-e-benchmark,3557.html">"Intel Core i7-4960X Review: Ivy Bridge-E, Benchmarked – Ivy Bridge-E: Core i7-4960X Gets Tested"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text"><cite id="CITEREFWasson2013" class="citation web cs1">Wasson, Scott (September 3, 2013). <a rel="nofollow" class="external text" href="http://techreport.com/review/25293/intel-core-i7-4960x-processor-reviewed/">"Intel's Core 4960X processor reviewed"</a>. <i>Tech Report</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-performance-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-performance_30-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFShimpi2012" class="citation web cs1">Shimpi, Anand Lal (March 6, 2012). <a rel="nofollow" class="external text" href="https://archive.today/20130101211311/http://www.anandtech.com/show/5626/ivy-bridge-preview-core-i7-3770k/">"The Ivy Bridge Preview: Core i7 3770K Tested"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/5626/ivy-bridge-preview-core-i7-3770k/">the original</a> on January 1, 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">May 25,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-heat-31"><span class="mw-cite-backlink">^ <a href="#cite_ref-heat_31-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-heat_31-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFTaylor2012" class="citation web cs1">Taylor, Billy (May 2, 2012). <a rel="nofollow" class="external text" href="http://www.tomshardware.com/news/ivy-bridge-overclocking-high-temp,15512.html">"Intel's Ivy Bridge Hotter Than Sandy Bridge When Overclocked"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></span>
</li>
<li id="cite_note-vr-zone-32"><span class="mw-cite-backlink">^ <a href="#cite_ref-vr-zone_32-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-vr-zone_32-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-vr-zone_32-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-vr-zone_32-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160304113344/http://vr-zone.com/articles/ivy-bridge-proven-to-suffer-from-poor-thermal-grease/15844.html">"Ivy Bridge proven to suffer from poor thermal grease by"</a>. <i>VR-Zone</i>. May 11, 2012. Archived from <a rel="nofollow" class="external text" href="http://vr-zone.com/articles/ivy-bridge-proven-to-suffer-from-poor-thermal-grease/15844.html">the original</a> on March 4, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">May 25,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-techpowerup-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-techpowerup_33-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.techpowerup.com/165882/TIM-is-Behind-Ivy-Bridge-Temperatures-After-All.html">"TIM is Behind Ivy Bridge Temperatures After All"</a>. <i>TechPowerUp</i>. May 12, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></span>
</li>
<li id="cite_note-cheapTIM-34"><span class="mw-cite-backlink">^ <a href="#cite_ref-cheapTIM_34-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-cheapTIM_34-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://news.softpedia.com/news/Intel-to-Officially-Enable-Better-Overclocking-in-Haswell-293719.shtml">"Intel to Officially Enable Better Overclocking in Haswell"</a>. <i>Softpedia News</i>. September 20, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-thermal2011-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-thermal2011_35-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFHagedoom2013" class="citation web cs1">Hagedoom, Hilbert (June 26, 2013). <a rel="nofollow" class="external text" href="https://www.guru3d.com/news-story/intel-ivy-bridge-e-has-solder-under-its-ihs.html">"Intel Ivy Bridge E has Solder Under Its IHS"</a>. <i>The Guru of 3D</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></span>
</li>
<li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><cite id="CITEREFHagan2012" class="citation web cs1">Hagan, Trace (May 11, 2012). <a rel="nofollow" class="external text" href="https://www.tweaktown.com/news/24059/">"Ivy Bridge's heat problem is indeed caused by Intel's TIM choice"</a>. <i>TweakTown</i>. US<span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-37">^</a></b></span> <span class="reference-text"><cite id="CITEREFWhiteFireDragon2012" class="citation web cs1">WhiteFireDragon (August 3, 2012). <a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=XXs0I5kuoX4">"Fixing Haswell and Ivy Bridge CPU temps: IHS removal"</a>. <i>YouTube</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 8,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text"><cite id="CITEREFLatif2012" class="citation web cs1 cs1-prop-unfit">Latif, Lawrence (April 30, 2012). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120505065428/http://www.theinquirer.net/inquirer/news/2171299/intel-admits-ivy-bridge-chips-run-hotter">"Intel admits Ivy Bridge chips run hotter"</a>. <i>The Inquirer</i>. Archived from the original on May 5, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">May 25,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-Intel_Datasheet-39"><span class="mw-cite-backlink">^ <a href="#cite_ref-Intel_Datasheet_39-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Intel_Datasheet_39-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Intel_Datasheet_39-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Intel_Datasheet_39-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-family-mobile-vol-1-datasheet.pdf">"Mobile 3rd Generation Intel Core Processor Family Datasheet"</a> <span class="cs1-format">(PDF)</span>. <i>Intel</i>. April 23, 2012.</cite></span>
</li>
<li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><cite id="CITEREFShimpiSmith2012" class="citation web cs1">Shimpi, Anand Lal; Smith, Ryan (April 23, 2012). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120424195906/http://www.anandtech.com/show/5771/the-intel-ivy-bridge-core-i7-3770k-review">"The Intel Ivy Bridge (Core i7 3770K) Review"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/5771/the-intel-ivy-bridge-core-i7-3770k-review">the original</a> on April 24, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">May 25,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-Ivy_Bridge_Modular_Design-42"><span class="mw-cite-backlink">^ <a href="#cite_ref-Ivy_Bridge_Modular_Design_42-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Ivy_Bridge_Modular_Design_42-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFGoto2012" class="citation web cs1 cs1-prop-foreign-lang-source">Goto, Hiroshige (February 22, 2012). <a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/docs/column/kaigai/20120222_513581.html">"Ivy Bridge Modular Design"</a>. <i>PC Watch</i> (in Japanese)<span class="reference-accessdate">. Retrieved <span class="nowrap">December 22,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-43">^</a></b></span> <span class="reference-text"><cite id="CITEREFShimpi2011" class="citation web cs1">Shimpi, Anand Lal (September 14, 2011). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110923191404/http://www.anandtech.com/show/4798/ivy-bridge-148b-transistors">"Ivy Bridge: 1.4B Transistors"</a>. <i>AnandTech</i>. Archived from <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4798/ivy-bridge-148b-transistors">the original</a> on September 23, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></span>
</li>
<li id="cite_note-44"><span class="mw-cite-backlink"><b><a href="#cite_ref-44">^</a></b></span> <span class="reference-text"><cite id="CITEREFCrowthers2012" class="citation web cs1">Crowthers, Doug (August 8, 2012). <a rel="nofollow" class="external text" href="http://www.tomshardware.com/news/Ivy_Bridge-E-LGA_2011-X79-cpu-mobo,16588.html">"Intel's Ivy Bridge-E set for Q3 2013, Shows Leaked Slide"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 12,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-45"><span class="mw-cite-backlink"><b><a href="#cite_ref-45">^</a></b></span> <span class="reference-text"><cite id="CITEREFPrickett_Morgan2013" class="citation news cs1">Prickett Morgan, Timothy (September 10, 2013). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2013/09/10/intel_ivy_bridge_xeon_e5_2600_v2_launch/">"Intel carves up Xeon E5-2600 v2 chips for two-socket boxes"</a>. <i>The Register</i><span class="reference-accessdate">. Retrieved <span class="nowrap">September 13,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-46"><span class="mw-cite-backlink"><b><a href="#cite_ref-46">^</a></b></span> <span class="reference-text"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://newsroom.intel.com/community/intel_newsroom/blog/2013/09/10/intel-introduces-highly-versatile-datacenter-processor-family-architected-for-new-era-of-services">"Intel Introduces Highly Versatile Datacenter Processor Family Architected for New Era of Services"</a>. <i>Intel Newsroom</i>. September 10, 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">September 13,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><cite id="CITEREFHearn2012" class="citation web cs1">Hearn, Mark (October 17, 2012). <a rel="nofollow" class="external text" href="https://www.engadget.com/2012/10/17/intel-roadmap-reveals-10-core-xeon-e5-2600-v2-cpu/">"Intel roadmap reveals 10-core Xeon E5-2600 V2 Ivy Bridge CPU"</a>. <i>Engadget</i><span class="reference-accessdate">. Retrieved <span class="nowrap">January 3,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-IB-E-legitreviews2-48"><span class="mw-cite-backlink">^ <a href="#cite_ref-IB-E-legitreviews2_48-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-IB-E-legitreviews2_48-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFS.2013" class="citation web cs1">S., Mike (January 3, 2013). <a rel="nofollow" class="external text" href="http://www.legitreviews.com/news/14815/">"Leak: Enthusiast-Grade IB-E CPUs Slated for Q3 along with SB-E Core i7-3980X 8 Core CPU for Q2"</a>. <i>Legit Reviews</i><span class="reference-accessdate">. Retrieved <span class="nowrap">January 23,</span> 2013</span>.</cite> (citing <a rel="nofollow" class="external text" href="http://wccftech.com/intels-leaked-roadmap-shows-ivy-bridgeepen-processors-12-cores-30mb-cache-130w-tdp/">an original post by Hassan Mujtaba on the same website</a>)</span>
</li>
<li id="cite_note-49"><span class="mw-cite-backlink"><b><a href="#cite_ref-49">^</a></b></span> <span class="reference-text"><cite id="CITEREFGasior2013" class="citation web cs1">Gasior, Geoff (April 1, 2013). <a rel="nofollow" class="external text" href="http://techreport.com/news/24591/leaked-slide-outs-ivy-bridge-e-models">"Leaked slide outs Ivy Bridge-E models"</a>. <i>Tech Report</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></span>
</li>
<li id="cite_note-CPU-World-IB-E2-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-CPU-World-IB-E2_50-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFShvets2013" class="citation web cs1">Shvets, Gennadiy (March 30, 2013). <a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2013/2013033001_Intel_Ivy_Bridge-E_extreme_CPUs_to_launch_in_Q3_2013.html">"Intel Ivy Bridge-E extreme CPUs to launch in Q3 2013"</a>. <i>CPU World</i><span class="reference-accessdate">. Retrieved <span class="nowrap">March 30,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-51">^</a></b></span> <span class="reference-text"><cite id="CITEREFRyan2014" class="citation web cs1">Ryan, Thomas (January 10, 2014). <a rel="nofollow" class="external text" href="http://www.semiaccurate.com/2014/01/10/intel-announces-xeon-e5-2400-v2-series-ces/">"Intel Announces the Xeon E5-2400 v2 Series at CES"</a>. <i>SemiAccurate</i><span class="reference-accessdate">. Retrieved <span class="nowrap">September 6,</span> 2024</span>.</cite></span>
</li>
<li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.v3.co.uk/v3-uk/news/2322218/intel-extends-xeon-e5-server-chip-family-with-e5-2400-v2-line-up">"Intel extends Xeon E5 server chip family with E5-2400 v2 line-up"</a>. <i>V3</i><span class="reference-accessdate">. Retrieved <span class="nowrap">January 21,</span> 2014</span>.</cite></span>
</li>
<li id="cite_note-Ivy_Bridge-E_processors_to_start_at_$310-53"><span class="mw-cite-backlink">^ <a href="#cite_ref-Ivy_Bridge-E_processors_to_start_at_$310_53-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Ivy_Bridge-E_processors_to_start_at_$310_53-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Ivy_Bridge-E_processors_to_start_at_$310_53-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFCyril_Kowaliski2013" class="citation web cs1">Cyril Kowaliski (August 1, 2013). <a rel="nofollow" class="external text" href="http://techreport.com/news/25168/report-ivy-bridge-e-processors-to-start-at-310">"Ivy Bridge-E processors to start at $310"</a>.</cite></span>
</li>
<li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/products/65523/Intel-Core-i7-3770K-Processor-%288M-Cache-up-to-3_90-GHz%29">"Intel Core i7-3770K Processor (8M Cache, up to 3.90 GHz)"</a>. Ark.intel.com<span class="reference-accessdate">. Retrieved <span class="nowrap">May 25,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-presence-pc-55"><span class="mw-cite-backlink">^ <a href="#cite_ref-presence-pc_55-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-presence-pc_55-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.engadget.com/2012/05/31/intel-dual-core-ivy-bridge/">"Intel details 14 dual-core Ivy Bridge processors ahead of Computex"</a>. May 31, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">September 30,</span> 2012</span>.</cite></span>
</li>
<li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.itworld.com/hardware/428779/intel-makes-custom-xeons-oracle">"Intel makes custom Xeons for Oracle"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">June 25,</span> 2014</span>.</cite></span>
</li>
<li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text"><cite id="CITEREFCunningham2013" class="citation web cs1">Cunningham, Andrew (January 14, 2013). <a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2013/01/the-technical-details-behind-intels-7-watt-ivy-bridge-cpus/">"The Technical Details Behind Intel's 7 Watt Ivy Bridge CPUs"</a>. <i>Ars Technica</i><span class="reference-accessdate">. Retrieved <span class="nowrap">January 14,</span> 2013</span>.</cite></span>
</li>
<li id="cite_note-haswell-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-haswell_58-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFCrothers2011" class="citation news cs1">Crothers, Brooke (September 14, 2011). <a rel="nofollow" class="external text" href="http://news.cnet.com/8301-13924_3-20106098-64/haswell-chip-completes-ultrabook-revolution/">"Haswell chip completes Ultrabook 'revolution'"</a>. <i>The Circuits Blog</i>. CNET.com<span class="reference-accessdate">. Retrieved <span class="nowrap">November 11,</span> 2011</span>.</cite></span>
</li>
<li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://support.microsoft.com/en-gb/help/3064209/june-2015-intel-cpu-microcode-update-for-windows">"June 2015 Intel CPU microcode update for Windows"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">November 7,</span> 2020</span>.</cite></span>
</li>
<li id="cite_note-60"><span class="mw-cite-backlink"><b><a href="#cite_ref-60">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.sevenforums.com/windows-updates-activation/373034-june-2015-microcode-update-intel-processors-windows.html">"Windows 7: June 2015 microcode update for Intel processors in Windows"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">November 7,</span> 2020</span>.</cite></span>
</li>
<li id="cite_note-61"><span class="mw-cite-backlink"><b><a href="#cite_ref-61">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://community.spiceworks.com/topic/1134840-windows-update-kb3064209-g3258-4010u">"Windows update KB3064209 (G3258 & 4010U)"</a>. August 19, 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">November 7,</span> 2020</span>.</cite></span>
</li>
</ol></div>
<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>
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<div class="side-box-text plainlist">Wikimedia Commons has media related to <span style="font-weight: bold; font-style: italic;"><a href="https://commons.wikimedia.org/wiki/Category:Ivy_Bridge_(microarchitecture)" class="extiw external" title="commons:Category:Ivy Bridge (microarchitecture)">Ivy Bridge (microarchitecture)</a></span>.</div></div>
</div>
<ul><li><cite id="CITEREFAngelini2012" class="citation web cs1">Angelini, Chris (April 23, 2012). <a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/ivy-bridge-benchmark-core-i7-3770k,3181.html">"Intel Core i7-3770K Review: A Small Step Up For Ivy Bridge"</a>. <i>Tom's Hardware</i>.</cite></li>
<li><cite id="CITEREFIntel2011" class="citation web cs1">Intel (May 4, 2011). <a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=YIkMaQJSyP8">"Video Animation: Mark Bohr Gets Small: 22 nm Explained"</a>. <i>YouTube</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 11,</span> 2011</span>.</cite></li>
<li><cite id="CITEREFKanter2012" class="citation web cs1">Kanter, David (April 22, 2012). <a rel="nofollow" class="external text" href="http://realworldtech.com/page.cfm?ArticleID=RWT042212225031">"Intel's Ivy Bridge Graphics Architecture"</a>. <i>Real World Tech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">April 24,</span> 2012</span>.</cite></li>
<li><cite id="CITEREFGavrichenkov2012" class="citation web cs1">Gavrichenkov, Ilya (September 19, 2012). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120923011411/http://www.xbitlabs.com/articles/cpu/display/core-i5-ivy-bridge.html">"Roundup: Intel Core i5 Processors with Ivy Bridge Microarchitecture"</a>. <i>X-bit Labs</i>. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/articles/cpu/display/core-i5-ivy-bridge.html">the original</a> on September 23, 2012.</cite></li>
<li><cite id="CITEREFGavrichenkov2012" class="citation web cs1">Gavrichenkov, Ilya (September 25, 2012). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120926234236/http://www.xbitlabs.com/articles/cpu/display/core-i3-ivy-bridge.html">"Roundup: Intel Core i3 Processors with Ivy Bridge Microarchitecture"</a>. <i>X-bit Labs</i>. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/articles/cpu/display/core-i3-ivy-bridge.html">the original</a> on September 26, 2012.</cite></li>
<li><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.supermicro.com/support/resources/memory/X9_DP_memory_config.pdf">"Memory Configuration Guide for X9 Series DP Motherboards – Revised Ivy Bridge Update (Socket R & B2)"</a> <span class="cs1-format">(PDF)</span>. <i>Super Micro Computer, Inc</i>. January 2014<span class="reference-accessdate">. Retrieved <span class="nowrap">November 27,</span> 2022</span>.</cite></li></ul>
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</style><div id="Intel_processors144" style="font-size:114%;margin:0 4em"><a href="List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="List_of_Intel_processors" title="List of Intel processors">Processors</a>
<ul><li><a href="List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li>
<li><a href="List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li>
<li><a href="List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a>
<ul><li><a href="List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li>
<li><a href="List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li>
<li><a href="List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li>
<li><a href="List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li>
<li><a href="List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li>
<li><a href="List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li>
<li><a href="List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a>
<ul><li><a href="List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li>
<li><a href="List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li>
<li><a href="List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li>
<li><a href="List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li>
<li><a href="List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li>
<li><a href="List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li>
<li><a href="List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li>
<li><a href="Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li>
<li><a href="List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li>
<li><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li>
<li><a href="List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li>
<li><a href="P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a>
<ul><li><a href="Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li>
<li><a href="Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li>
<li><a href="NetBurst" title="NetBurst">NetBurst</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a>
<ul><li><a href="Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li>
<li><a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>
<ul><li><a href="Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li>
<li><a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>
<ul></ul></li>
<li><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>
<ul><li><a href="Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li>
<li><a href="Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>
<ul><li><a href="Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li>
<li><a href="Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a>
<ul><li><a href="Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li>
<li><a href="Willow_Cove" title="Willow Cove">Willow Cove</a></li>
<li><a href="Golden_Cove" title="Golden Cove">Golden Cove</a>
<ul><li><a href="Raptor_Cove" class="mw-redirect" title="Raptor Cove">Raptor Cove</a></li></ul></li>
<li>Redwood Cove</li>
<li><a href="Lion_Cove" title="Lion Cove">Lion Cove</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86" title="X86">x86</a> <a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>
<ul><li><a href="Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li>
<li><a href="Silvermont" title="Silvermont">Silvermont</a></li></ul></li>
<li><a href="Goldmont" title="Goldmont">Goldmont</a>
<ul><li><a href="Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li>
<li><a href="Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>
<ul><li><a href="Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li>
<li>Crestmont</li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_Atom" title="Intel Atom">Atom</a></li>
<li><a href="Celeron" title="Celeron">Celeron</a></li>
<li><a href="Pentium" title="Pentium">Pentium</a></li>
<li><a href="Intel_Core" title="Intel Core">Core</a>
<ul><li><a href="Intel_Core#10th_generation" title="Intel Core">10th gen</a></li>
<li><a href="Intel_Core#11th_generation" title="Intel Core">11th gen</a></li>
<li><a href="Intel_Core#12th_generation" title="Intel Core">12th gen</a></li>
<li><a href="Intel_Core#13th_generation" title="Intel Core">13th gen</a></li>
<li><a href="Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li>
<li><a href="Intel_Core#Core_and_Core_Ultra_3/5/7/9" title="Intel Core">Core Ultra</a>
<ul><li><a href="Intel_Core#Series_1" title="Intel Core">1st gen</a></li>
<li><a href="Intel_Core#Series_2" title="Intel Core">2nd gen</a></li></ul></li>
<li><a href="Xeon" title="Xeon">Xeon</a></li></ul>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_4004" title="Intel 4004">4004</a> (1971)</li>
<li><a href="Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_8008" title="Intel 8008">8008</a> (1972)</li>
<li><a href="Intel_8080" title="Intel 8080">8080</a> (1974)</li>
<li><a href="Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="X86" title="X86">x86</a> (<a href="16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_8086" title="Intel 8086">8086</a> (1978)</li>
<li><a href="Intel_8088" title="Intel 8088">8088</a> (1979)</li>
<li><a href="Intel_80186" title="Intel 80186">80186</a> (1982)</li>
<li><a href="Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li>
<li><a href="Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X87" title="X87">x87</a> (external <a href="Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<dl><dt>8/16-bit databus</dt>
<dd><a href="Intel_8087" title="Intel 8087">8087</a> (1980)</dd>
<dt>16-bit databus</dt>
<dd><a href="Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd>
<dd><a href="Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd>
<dd><a href="Intel_80387SX" title="Intel 80387SX">80387SX</a></dd>
<dt>32-bit databus</dt>
<dd><a href="Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd>
<dd><a href="Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="I386" title="I386">i386</a>
<ul><li><a href="Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li>
<li><a href="Intel_80376" title="Intel 80376">376</a></li>
<li><a href="Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li>
<li><a href="I486" title="I486">i486</a>
<ul><li><a href="I486SX" title="I486SX">SX</a></li>
<li><a href="Intel_DX2" title="Intel DX2">DX2</a></li>
<li><a href="Intel_DX4" title="Intel DX4">DX4</a></li>
<li><a href="I486SL" title="I486SL">SL</a></li>
<li><a href="RapidCAD" title="RapidCAD">RapidCAD</a></li>
<li><a href="I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li>
<li><a href="Stealey" title="Stealey">A100/A110</a></li>
<li><a href="Intel_Atom" title="Intel Atom">Atom</a>
<ul><li><a href="List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li>
<li><a href="Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li>
<li><a href="Celeron" title="Celeron">Celeron</a> (1998)
<ul><li><a href="Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li>
<li><a href="Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li>
<li><a href="Pentium" title="Pentium">Pentium</a>
<ul><li><a href="Pentium_(original)" title="Pentium (original)">Original i586</a></li>
<li><a href="Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li>
<li><a href="Pentium_Pro" title="Pentium Pro">Pro</a></li>
<li><a href="Pentium_II" title="Pentium II">II</a></li>
<li><a href="Pentium_III" title="Pentium III">III</a></li>
<li><a href="Pentium_4" title="Pentium 4">4</a></li>
<li><a href="Pentium_M" title="Pentium M">M</a></li>
<li><a href="Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li>
<li><a href="Intel_Core" title="Intel Core">Core</a></li>
<li><a href="Xeon" title="Xeon">Xeon</a>
<ul><li><a href="List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li>
<li><a href="List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li>
<li><a href="List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li>
<li><a href="Intel_Quark" title="Intel Quark">Quark</a></li>
<li><a href="Tolapai" title="Tolapai">Tolapai</a></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Intel_Atom" title="Intel Atom">Atom</a>
<ul><li><a href="Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li>
<li><a href="List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li>
<li><a href="Celeron" title="Celeron">Celeron</a>
<ul><li><a href="Celeron#Prescott-256" title="Celeron">D</a></li>
<li><a href="Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li>
<li><a href="Pentium" title="Pentium">Pentium</a>
<ul><li><a href="Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li>
<li><a href="Pentium_D" title="Pentium D">D</a></li>
<li><a href="Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li>
<li><a href="Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li>
<li><a href="Intel_Core" title="Intel Core">Core</a>
<ul><li><a href="Intel_Core_2" title="Intel Core 2">2</a></li>
<li><a href="Intel_Core#1st_generation" title="Intel Core">1st gen</a></li>
<li><a href="Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li>
<li><a href="Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li>
<li><a href="Intel_Core#4th_generation" title="Intel Core">4th gen</a></li>
<li><a href="Intel_Core#5th_generation" title="Intel Core">5th gen</a></li>
<li><a href="Intel_Core#6th_generation" title="Intel Core">6th gen</a></li>
<li><a href="Intel_Core#7th_generation" title="Intel Core">7th gen</a></li>
<li><a href="Intel_Core#8th_generation" title="Intel Core">8th gen</a></li>
<li><a href="Intel_Core#9th_generation" title="Intel Core">9th gen</a></li>
<li><a href="Intel_Core#10th_generation" title="Intel Core">10th gen</a></li>
<li><a href="Intel_Core#11th_generation" title="Intel Core">11th gen</a></li>
<li><a href="List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li>
<li><a href="Xeon" title="Xeon">Xeon</a>
<ul><li><a href="List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li>
<li><a href="List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li>
<li><a href="List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li>
<li><a href="List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li>
<li><a href="List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li>
<li><a href="List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul>
</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">
<dl><dt><a href="Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt>
<dd><a href="Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd>
<dt><a href="Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt>
<dd><a href="Itanium" title="Itanium">Itanium</a></dd>
<dt><a href="Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt>
<dd><a href="Intel_i860" title="Intel i860">i860</a></dd>
<dd><a href="Intel_i960" title="Intel i960">i960</a></dd>
<dd><a href="StrongARM" title="StrongARM">StrongARM</a></dd>
<dd><a href="XScale" title="XScale">XScale</a></dd></dl>
</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">
<ul><li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>
<li><a href="Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li>
<li><a href="List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a>
<ul><li><a href="Intel_GMA" title="Intel GMA">GMA</a></li>
<li><a href="Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li>
<li><a href="Intel_Xe" title="Intel Xe">Xe</a></li>
<li><a href="Intel_Arc" title="Intel Arc">Arc</a></li></ul></li>
<li><a href="Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li>
<li><a href="System_Controller_Hub" title="System Controller Hub">SCHs</a></li>
<li><a href="I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li>
<li><a href="PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li>
<li><a href="Stratix" title="Stratix">Stratix</a></li>
<li><a href="List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li>
<li><a href="Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul>
</div></td></tr></tbody></table></div>
<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Intel_CPU_core_roadmaps_from_P6_to_Panther_Lake74" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Intel_CPU_core_roadmaps_from_P6_to_Panther_Lake74" style="font-size:114%;margin:0 4em">Intel CPU core roadmaps from <a href="P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> to Panther Lake</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"><table class="wikitable" style="border:none; text-align:center;">
<tbody><tr>
<th colspan="2" style="background-color:var(--background-color-progressive-subtle);"><a href="Intel_Atom" title="Intel Atom"><span style="color:var(--color-progressive);">Atom (ULV)</span></a></th>
<td rowspan="39" style="border:none; background-color:var(--background-color-base);"></td>
<th rowspan="2">Node name</th>
<td rowspan="39" style="border:none; background-color:var(--background-color-base);"></td>
<th colspan="2" style="background-color:var(--background-color-progressive-subtle); color:var(--color-base);"><a href="Pentium" title="Pentium"><span style="color:var(--color-progressive);">Pentium</span></a>/<a href="Intel_Core" title="Intel Core"><span style="color:var(--color-progressive);">Core</span></a></th>
<td rowspan="39" style="border:none; background-color:var(--background-color-base);"></td>
<td colspan="5" rowspan="7" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<th style="background-color:var(--background-color-progressive-subtle);"><a href="Microarchitecture" title="Microarchitecture"><span style="color:var(--color-progressive);">Microarch.</span></a></th>
<th style="background-color:var(--background-color-progressive-subtle); color:var(--color-base);">Step</th>
<th style="background-color:var(--background-color-progressive-subtle);"><a href="Microarchitecture" title="Microarchitecture"><span style="color:var(--color-progressive);">Microarch.</span></a></th>
<th style="background-color:var(--background-color-progressive-subtle); color:var(--color-base);">Step</th>
</tr>
<tr>
<td colspan="2" rowspan="13"></td>
<th><a href="600_nm_process" title="600 nm process">600 nm</a></th>
<td rowspan="8"><b><a href="P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a></b></td>
<td><a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a><br>(133 MHz)</td>
</tr>
<tr>
<th><a href="600_nm_process" title="600 nm process">500 nm</a></th>
<td><a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a><br>(150 MHz)</td>
</tr>
<tr>
<th rowspan="2"><a href="350_nm_process" title="350 nm process">350 nm</a></th>
<td><a href="Pentium_Pro" title="Pentium Pro">Pentium Pro</a><br>(166–200 MHz)</td>
</tr>
<tr>
<td><a href="Klamath_(microprocessor)" class="mw-redirect" title="Klamath (microprocessor)">Klamath</a></td>
</tr>
<tr>
<th rowspan="2"><a href="250_nm_process" title="250 nm process">250 nm</a></th>
<td><a href="Deschutes_(microprocessor)" class="mw-redirect" title="Deschutes (microprocessor)">Deschutes</a></td>
</tr>
<tr>
<td><a href="Katmai_(microprocessor)" class="mw-redirect" title="Katmai (microprocessor)">Katmai</a></td>
<th style="background-color:var(--background-color-progressive-subtle);"><a href="NetBurst" title="NetBurst"><span style="color:var(--color-progressive);">NetBurst</span></a></th>
<td colspan="4" rowspan="3" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<th><a href="180_nm_process" title="180 nm process">180 nm</a></th>
<td><a href="Coppermine_(microprocessor)" class="mw-redirect" title="Coppermine (microprocessor)">Coppermine</a></td>
<td><a href="Pentium_4#Willamette" title="Pentium 4">Willamette</a></td>
</tr>
<tr>
<th rowspan="2"><a href="130_nm_process" title="130 nm process">130 nm</a></th>
<td><a href="Tualatin_(microprocessor)" class="mw-redirect" title="Tualatin (microprocessor)">Tualatin</a></td>
<td rowspan="2"><a href="Pentium_4#Northwood" title="Pentium 4">Northwood</a></td>
</tr>
<tr>
<td rowspan="4"><b>Pentium M</b></td>
<td><a href="Banias_(microprocessor)" class="mw-redirect" title="Banias (microprocessor)">Banias</a></td>
<td style="border:none; background-color:var(--background-color-base);"></td>
<th style="background-color:var(--background-color-progressive-subtle);"><a href="Hyper-threading" title="Hyper-threading"><span style="color:var(--color-progressive);">NetBurst(HT)</span></a></th>
<td style="border:none; background-color:var(--background-color-base);"></td>
<th style="background-color:var(--background-color-progressive-subtle); color:var(--color-base);">NetBurst(<a href="Multi-core_processor" title="Multi-core processor"><span style="color:var(--color-progressive);">×2</span></a>)</th>
</tr>
<tr>
<th rowspan="2"><a href="90_nm_process" title="90 nm process">90 nm</a></th>
<td rowspan="2"><a href="Dothan_(microprocessor)" class="mw-redirect" title="Dothan (microprocessor)">Dothan</a></td>
<td><a href="Pentium_4#Prescott" title="Pentium 4">Prescott</a></td>
<td style="border:none; background-color:var(--background-color-base); color:var(--color-base);">⇨</td>
<td><a href="Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">Prescott‑2M</a></td>
<td style="border:none; background-color:var(--background-color-base); color:var(--color-base);">⇨</td>
<td><a href="Smithfield_(microprocessor)" class="mw-redirect" title="Smithfield (microprocessor)">Smithfield</a></td>
</tr>
<tr>
<td><s><a href="Tejas_and_Jayhawk" title="Tejas and Jayhawk">Tejas</a></s></td>
<td style="border:none; background-color:var(--background-color-base); color:var(--color-base);">→</td>
<td>⇩</td>
<td style="border:none; background-color:var(--background-color-base); color:var(--color-base);">→</td>
<td><s><a href="Tejas_and_Jayhawk#Design_and_microarchitecture" title="Tejas and Jayhawk">Cedarmill (Tejas)</a></s></td>
</tr>
<tr>
<th rowspan="2"><a href="65_nm_process" title="65 nm process">65 nm</a></th>
<td><a href="Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a></td>
<td><s><a href="NetBurst#Successor" title="NetBurst">Nehalem (NetBurst)</a></s></td>
<td style="border:none; background-color:var(--background-color-base);"></td>
<td><a href="Pentium_4#Cedar_Mill" title="Pentium 4">Cedar Mill</a></td>
<td style="border:none; background-color:var(--background-color-base); color:var(--color-base);">⇨</td>
<td><a href="Presler_(microprocessor)" class="mw-redirect" title="Presler (microprocessor)">Presler</a></td>
</tr>
<tr>
<td rowspan="2"><b>Core</b></td>
<td><a href="Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Merom</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">4 cores on mainstream desktop, <a href="DDR3" class="mw-redirect" title="DDR3">DDR3</a> introduced</td>
</tr>
<tr>
<td rowspan="4"><b>Bonnell</b></td>
<td rowspan="2"><a href="Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a></td>
<th rowspan="2"><a href="45_nm_process" title="45 nm process">45 nm</a></th>
<td><a href="Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<td rowspan="2"><b>Nehalem</b></td>
<td><a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);"><a href="Hyper-threading" title="Hyper-threading">HT</a> reintroduced, integrated <a href="Memory_controller" title="Memory controller">MC</a>, PCH<br>L3-cache introduced, 256KB L2-cache/core</td>
</tr>
<tr>
<td rowspan="2"><a href="Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></td>
<th rowspan="2"><a href="32_nm_process" title="32 nm process">32 nm</a></th>
<td><a href="Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">Introduced GPU on same package and <a href="AES-NI" class="mw-redirect" title="AES-NI">AES-NI</a></td>
</tr>
<tr>
<td rowspan="2"><b>Sandy Bridge</b></td>
<td><a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">On-die ring bus, no more non-<a href="UEFI" title="UEFI">UEFI</a> motherboards</td>
</tr>
<tr>
<td rowspan="4"><b>Silvermont</b></td>
<td rowspan="2"><a href="Silvermont" title="Silvermont">Silvermont</a></td>
<th rowspan="2"><a href="22_nm_process" title="22 nm process">22 nm</a></th>
<td></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<td rowspan="2"><b>Haswell</b></td>
<td><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">Fully integrated voltage regulator</td>
</tr>
<tr>
<td rowspan="2"><a href="Airmont_(microarchitecture)" class="mw-redirect" title="Airmont (microarchitecture)">Airmont</a></td>
<th rowspan="9"><a href="14_nm_process" title="14 nm process">14 nm</a></th>
<td><a href="Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<td rowspan="7"><b>Skylake</b></td>
<td><a href="Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);"><a href="DDR4" class="mw-redirect" title="DDR4">DDR4</a> introduced on mainstream desktop</td>
</tr>
<tr>
<td rowspan="3"><b>Goldmont</b></td>
<td rowspan="3"><a href="Goldmont" title="Goldmont">Goldmont</a></td>
<td><a href="Kaby_Lake" title="Kaby Lake">Kaby Lake</a></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<td><a href="Coffee_Lake" title="Coffee Lake">Coffee Lake</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">6 cores on mainstream desktop</td>
</tr>
<tr>
<td><a href="Kaby_Lake#Amber_Lake" title="Kaby Lake">Amber Lake</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">Mobile-only</td>
</tr>
<tr>
<td rowspan="4"><b>Goldmont Plus</b></td>
<td rowspan="4"><a href="Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></td>
<td><a href="Whiskey_Lake" title="Whiskey Lake">Whiskey Lake</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">Mobile-only</td>
</tr>
<tr>
<td><a href="Coffee_Lake" title="Coffee Lake">Coffee Lake</a> Refresh</td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">8 cores on mainstream desktop</td>
</tr>
<tr>
<td><a href="Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a></td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">10 cores on mainstream desktop</td>
</tr>
<tr>
<td><b>Sunny Cove</b></td>
<td><a href="Sunny_Cove_(microarchitecture)#Cypress_Cove" title="Sunny Cove (microarchitecture)">Cypress Cove</a> (<a href="Rocket_Lake" title="Rocket Lake">Rocket Lake</a>)</td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);">Backported Sunny Cove microarchitecture for 14nm</td>
</tr>
<tr>
<td rowspan="3"><b>Tremont</b></td>
<td rowspan="3"><a href="Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a></td>
<th rowspan="3"><a href="10_nm_process" title="10 nm process">10 nm</a></th>
<td><b>Skylake</b></td>
<td>Palm Cove (<a href="Cannon_Lake_(microarchitecture)" class="mw-redirect" title="Cannon Lake (microarchitecture)">Cannon Lake</a>)</td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">Mobile-only</td>
</tr>
<tr>
<td rowspan="2"><b>Sunny Cove</b></td>
<td><a href="Sunny_Cove" class="mw-redirect" title="Sunny Cove">Sunny Cove</a> (<a href="Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a>)</td>
<td colspan="5" style="text-align:left; color:var(--color-base); border:none; background-color:var(--background-color-base);">512 KB L2-cache/core</td>
</tr>
<tr>
<td><a href="Willow_Cove" title="Willow Cove">Willow Cove</a> (<a href="Tiger_Lake" title="Tiger Lake">Tiger Lake</a>)</td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);"><a href="Intel_Xe" title="Intel Xe">X<sup>e</sup></a> graphics engine</td>
</tr>
<tr>
<td rowspan="2"><b>Gracemont</b></td>
<td rowspan="2"><a href="Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></td>
<th rowspan="2"><a href="7_nm_process" title="7 nm process">Intel 7</a><br>(10nm ESF)</th>
<td rowspan="2"><b>Golden Cove</b></td>
<td><a href="Golden_Cove" title="Golden Cove">Golden Cove</a> (<a href="Alder_Lake" title="Alder Lake">Alder Lake</a>)</td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);">Hybrid, DDR5, PCIe 5.0</td>
</tr>
<tr>
<td><a href="Golden_Cove#Raptor_Cove" title="Golden Cove">Raptor Cove</a> (<a href="Raptor_Lake" title="Raptor Lake">Raptor Lake</a>)</td>
<td colspan="5" style="border:none; background-color:var(--background-color-base);"></td>
</tr>
<tr>
<td rowspan="2"><b>Crestmont</b></td>
<td rowspan="2">Crestmont</td>
<th><a href="5_nm_process" title="5 nm process">Intel 4</a></th>
<td rowspan="2"><b>Redwood Cove</b></td>
<td><a href="Meteor_Lake" title="Meteor Lake">Meteor Lake</a></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);">Mobile-only<br><a href="Neural_processing_unit" title="Neural processing unit">NPU</a>, <a href="Chiplet" title="Chiplet">chiplet</a> architecture</td>
</tr>
<tr>
<th><a href="3_nm_process" title="3 nm process">Intel 3</a></th>
<td><a href="Arrow_Lake_(microprocessor)" title="Arrow Lake (microprocessor)">Arrow Lake-U</a></td>
</tr>
<tr>
<td rowspan="2"><b>Skymont</b></td>
<td rowspan="2"><i>Skymont</i></td>
<th rowspan="2"><a href="3_nm_process" title="3 nm process">N3B</a> (<a href="TSMC" title="TSMC">TSMC</a>)</th>
<td rowspan="2"><b>Lion Cove</b></td>
<td><i><a href="Lunar_Lake" title="Lunar Lake">Lunar Lake</a></i></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);">Low power mobile only (9-30W) </td>
</tr>
<tr>
<td><i><a href="Arrow_Lake_(microprocessor)" title="Arrow Lake (microprocessor)">Arrow Lake</a></i></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);"></td>
</tr>
<tr>
<td><b>Darkmont</b></td>
<td><i>Darkmont</i></td>
<td></td>
<td><a href="2_nm_process" title="2 nm process">Intel 18A</a></td>
<td></td>
<td><b>Cougar Cove</b></td>
<td><i><a href="Panther_Lake_(microprocessor)" title="Panther Lake (microprocessor)">Panther Lake</a></i></td>
<td colspan="5" style="border:none; background-color:var(--background-color-base); text-align:left; color:var(--color-base);"></td>
</tr>
</tbody></table>
<ul style="text-align:left;">
<li><s>Strike-through</s> indicates cancelled processors
</li><li><b>Bold names</b> are microarchitectures
</li><li><i>Italic names</i> are future processors
</li></ul></div></td></tr></tbody></table></div></div><!--htdig_noindex--><div><div class="zim-footer">
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